utility.hh (7707:e5b6f1157be3) | utility.hh (7720:65d338a8dba4) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31#ifndef __ARCH_SPARC_UTILITY_HH__ 32#define __ARCH_SPARC_UTILITY_HH__ 33 34#include "arch/sparc/isa_traits.hh" 35#include "arch/sparc/registers.hh" 36#include "arch/sparc/tlb.hh" 37#include "base/misc.hh" 38#include "base/bitfield.hh" | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31#ifndef __ARCH_SPARC_UTILITY_HH__ 32#define __ARCH_SPARC_UTILITY_HH__ 33 34#include "arch/sparc/isa_traits.hh" 35#include "arch/sparc/registers.hh" 36#include "arch/sparc/tlb.hh" 37#include "base/misc.hh" 38#include "base/bitfield.hh" |
39#include "cpu/static_inst.hh" |
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39#include "cpu/thread_context.hh" 40#include "sim/fault.hh" 41 42namespace SparcISA 43{ | 40#include "cpu/thread_context.hh" 41#include "sim/fault.hh" 42 43namespace SparcISA 44{ |
45 46 inline PCState 47 buildRetPC(const PCState &curPC, const PCState &callPC) 48 { 49 PCState ret = callPC; 50 ret.uEnd(); 51 ret.pc(curPC.npc()); 52 return ret; 53 } 54 |
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44 uint64_t 45 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 46 47 static inline bool 48 inUserMode(ThreadContext *tc) 49 { 50 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) || 51 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2))); --- 21 unchanged lines hidden (view full) --- 73 } 74 75 void copyRegs(ThreadContext *src, ThreadContext *dest); 76 77 void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 78 79 void skipFunction(ThreadContext *tc); 80 | 55 uint64_t 56 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 57 58 static inline bool 59 inUserMode(ThreadContext *tc) 60 { 61 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) || 62 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2))); --- 21 unchanged lines hidden (view full) --- 84 } 85 86 void copyRegs(ThreadContext *src, ThreadContext *dest); 87 88 void copyMiscRegs(ThreadContext *src, ThreadContext *dest); 89 90 void skipFunction(ThreadContext *tc); 91 |
92 inline void 93 advancePC(PCState &pc, const StaticInstPtr inst) 94 { 95 inst->advancePC(pc); 96 } 97 |
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81} // namespace SparcISA 82 83#endif | 98} // namespace SparcISA 99 100#endif |