1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38#include "base/bitfield.hh"
39#include "cpu/static_inst.hh"
40#include "cpu/thread_context.hh"
41#include "sim/fault.hh"
42
43namespace SparcISA
44{
45
46 inline PCState
47 buildRetPC(const PCState &curPC, const PCState &callPC)
48 {
49 PCState ret = callPC;
50 ret.uEnd();
51 ret.pc(curPC.npc());
52 return ret;
53 }
54
55 uint64_t
56 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
57
58 static inline bool
59 inUserMode(ThreadContext *tc)
60 {
61 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
62 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
63 }
64
65 /**
66 * Function to insure ISA semantics about 0 registers.
67 * @param tc The thread context.
68 */
69 template <class TC>
70 void zeroRegisters(TC *tc);
71
72 void initCPU(ThreadContext *tc, int cpuId);
73
74 inline void
75 startupCPU(ThreadContext *tc, int cpuId)
76 {
77#if FULL_SYSTEM
78 // Other CPUs will get activated by IPIs
79 if (cpuId == 0)
80 tc->activate(0);
81#else
82 tc->activate(0);
83#endif
84 }
85
86 void copyRegs(ThreadContext *src, ThreadContext *dest);
87
88 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
89
90 void skipFunction(ThreadContext *tc);
91
92 inline void
93 advancePC(PCState &pc, const StaticInstPtr inst)
94 {
95 inst->advancePC(pc);
96 }
97
98} // namespace SparcISA
99
100#endif