1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
34#include "arch/sparc/isa_traits.hh"
35#include "base/misc.hh"
36#include "base/bitfield.hh"
37#include "cpu/thread_context.hh"
38
39namespace SparcISA
40{
41 inline ExtMachInst

--- 52 unchanged lines hidden (view full) ---

94
95 /**
96 * Function to insure ISA semantics about 0 registers.
97 * @param tc The thread context.
98 */
99 template <class TC>
100 void zeroRegisters(TC *tc);
101
102 void initCPU(ThreadContext *tc, int cpuId)
103 {
104 //This would be a good place to stick a PowerOnReset fault into the
105 //cpu.
106 }
107
108} // namespace SparcISA
109
110#endif