1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34#include "arch/sparc/isa_traits.hh"
35#include "arch/sparc/registers.hh"
36#include "arch/sparc/tlb.hh"
37#include "base/bitfield.hh"
38#include "base/misc.hh"
39#include "cpu/static_inst.hh"
40#include "cpu/thread_context.hh"
41#include "sim/fault_fwd.hh"
42#include "sim/full_system.hh"
43
44namespace SparcISA
45{
46
47inline PCState
48buildRetPC(const PCState &curPC, const PCState &callPC)
49{
50 PCState ret = callPC;

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69template <class TC>
70void zeroRegisters(TC *tc);
71
72void initCPU(ThreadContext *tc, int cpuId);
73
74inline void
75startupCPU(ThreadContext *tc, int cpuId)
76{
77 // Other CPUs will get activated by IPIs
78 if (cpuId == 0 || !FullSystem)
79 tc->activate(0);
80}
81
82void copyRegs(ThreadContext *src, ThreadContext *dest);
83
84void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
85
86void skipFunction(ThreadContext *tc);
87

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