1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38#include "base/bitfield.hh"
39#include "cpu/static_inst.hh"
40#include "cpu/thread_context.hh"
41#include "sim/fault.hh"
42
43namespace SparcISA
44{
45
46inline PCState
47buildRetPC(const PCState &curPC, const PCState &callPC)
48{
49 PCState ret = callPC;
50 ret.uEnd();
51 ret.pc(curPC.npc());
52 return ret;
53}
54
55uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
56
57static inline bool
58inUserMode(ThreadContext *tc)
59{
60 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
61 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
62}
63
64/**
65 * Function to insure ISA semantics about 0 registers.
66 * @param tc The thread context.
67 */
68template
69void zeroRegisters(TC *tc);
70
71void initCPU(ThreadContext *tc, int cpuId);
72
73inline void
74startupCPU(ThreadContext *tc, int cpuId)
75{
76#if FULL_SYSTEM
77 // Other CPUs will get activated by IPIs
78 if (cpuId == 0)
79 tc->activate(0);
80#else
81 tc->activate(0);
82#endif
83}
84
85void copyRegs(ThreadContext *src, ThreadContext *dest);
86
87void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
88
89void skipFunction(ThreadContext *tc);
90
91inline void
92advancePC(PCState &pc, const StaticInstPtr inst)
93{
94 inst->advancePC(pc);
95}
96
97} // namespace SparcISA
98
99#endif