1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
34#include "arch/sparc/isa_traits.hh"
35#include "arch/sparc/registers.hh"
36#include "arch/sparc/tlb.hh"
37#include "base/misc.hh"
38#include "base/bitfield.hh"
39#include "cpu/thread_context.hh"
40#include "sim/fault.hh"
41
42namespace SparcISA
43{
44 uint64_t getArgument(ThreadContext *tc, int number, bool fp);
45
46 static inline bool
47 inUserMode(ThreadContext *tc)
48 {
49 return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
50 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
51 }
52
53 /**
54 * Function to insure ISA semantics about 0 registers.
55 * @param tc The thread context.
56 */
57 template <class TC>
58 void zeroRegisters(TC *tc);
59
60 void initCPU(ThreadContext *tc, int cpuId);
61
62 inline void
63 startupCPU(ThreadContext *tc, int cpuId)
64 {
65#if FULL_SYSTEM
66 // Other CPUs will get activated by IPIs
67 if (cpuId == 0)
68 tc->activate(0);
69#else
70 tc->activate(0);
71#endif
72 }
73
74 void copyRegs(ThreadContext *src, ThreadContext *dest);
75
76 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
77
78} // namespace SparcISA
79
80#endif