1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_SPARC_UTILITY_HH__
32#define __ARCH_SPARC_UTILITY_HH__
33
34#include "arch/sparc/faults.hh"
35#include "arch/sparc/isa_traits.hh"
36#include "base/misc.hh"
37#include "base/bitfield.hh"
38#include "cpu/thread_context.hh"
39
40namespace SparcISA
41{
42 inline ExtMachInst

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95
96 /**
97 * Function to insure ISA semantics about 0 registers.
98 * @param tc The thread context.
99 */
100 template <class TC>
101 void zeroRegisters(TC *tc);
102
103 inline void initCPU(ThreadContext *tc, int cpuId)
104 {
105 static Fault por = new PowerOnReset();
106 por->invoke(tc);
107 }
108
109} // namespace SparcISA
110
111#endif