ua2005.cc (8232:b28d06a175be) ua2005.cc (8747:017e5bbbb4e2)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 193 unchanged lines hidden (view full) ---

202 cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1));
203 }
204 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
205 break;
206
207 case MISCREG_HPSTATE:
208 // T1000 spec says impl. dependent val must always be 1
209 setMiscRegNoEffect(miscReg, val | HPSTATE::id);
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 193 unchanged lines hidden (view full) ---

202 cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1));
203 }
204 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
205 break;
206
207 case MISCREG_HPSTATE:
208 // T1000 spec says impl. dependent val must always be 1
209 setMiscRegNoEffect(miscReg, val | HPSTATE::id);
210#if FULL_SYSTEM
211 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
212 cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
213 else
214 cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
210 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
211 cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
212 else
213 cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
215#endif
216 break;
217 case MISCREG_HTSTATE:
218 setMiscRegNoEffect(miscReg, val);
219 break;
220
221 case MISCREG_STRAND_STS_REG:
222 if (bits(val,2,2))
223 panic("No support for setting spec_en bit\n");
224 setMiscRegNoEffect(miscReg, bits(val,0,0));
225 if (!bits(val,0,0)) {
226 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
227 // Time to go to sleep
228 tc->suspend();
214 break;
215 case MISCREG_HTSTATE:
216 setMiscRegNoEffect(miscReg, val);
217 break;
218
219 case MISCREG_STRAND_STS_REG:
220 if (bits(val,2,2))
221 panic("No support for setting spec_en bit\n");
222 setMiscRegNoEffect(miscReg, bits(val,0,0));
223 if (!bits(val,0,0)) {
224 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
225 // Time to go to sleep
226 tc->suspend();
227#if FULL_SYSTEM
229 if (tc->getKernelStats())
230 tc->getKernelStats()->quiesce();
228 if (tc->getKernelStats())
229 tc->getKernelStats()->quiesce();
230#endif
231 }
232 break;
233
234 default:
235 panic("Invalid write to FS misc register %s\n",
236 getMiscRegName(miscReg));
237 }
238}

--- 133 unchanged lines hidden --- 		231 }
232 break;
233
234 default:
235 panic("Invalid write to FS misc register %s\n",
236 getMiscRegName(miscReg));
237 }
238}

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