ua2005.cc (6335:a08470cb53e5) ua2005.cc (7741:340b6f01d69b)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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58 for (int bit = 15; bit > 0; --bit) {
59 if (1 << bit & softint && bit > pil)
60 cpu->postInterrupt(IT_SOFT_INT, bit);
61 else
62 cpu->clearInterrupt(IT_SOFT_INT, bit);
63 }
64}
65
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 49 unchanged lines hidden (view full) ---

58 for (int bit = 15; bit > 0; --bit) {
59 if (1 << bit & softint && bit > pil)
60 cpu->postInterrupt(IT_SOFT_INT, bit);
61 else
62 cpu->clearInterrupt(IT_SOFT_INT, bit);
63 }
64}
65
66//These functions map register indices to names
66// These functions map register indices to names
67static inline string
68getMiscRegName(RegIndex index)
69{
70 static string miscRegName[NumMiscRegs] =
71 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
72 "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
73 "stick", "stick_cmpr",
74 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",

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262
263 case MISCREG_HTBA:
264 return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF);
265 case MISCREG_HVER:
266 // XXX set to match Legion
267 return ULL(0x3e) << 48 |
268 ULL(0x23) << 32 |
269 ULL(0x20) << 24 |
67static inline string
68getMiscRegName(RegIndex index)
69{
70 static string miscRegName[NumMiscRegs] =
71 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
72 "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
73 "stick", "stick_cmpr",
74 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",

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262
263 case MISCREG_HTBA:
264 return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF);
265 case MISCREG_HVER:
266 // XXX set to match Legion
267 return ULL(0x3e) << 48 |
268 ULL(0x23) << 32 |
269 ULL(0x20) << 24 |
270 //MaxGL << 16 | XXX For some reason legion doesn't set GL
270 // MaxGL << 16 | XXX For some reason legion doesn't set GL
271 MaxTL << 8 |
272 (NWindows -1) << 0;
273
274 case MISCREG_STRAND_STS_REG:
275 System *sys;
276 int x;
277 sys = tc->getSystemPtr();
278

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329 assert(ticks >= 0 && "stick compare missed interrupt cycle");
330
331 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
332 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
333 (stick_cmpr & mask(63)));
334 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
335 setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
336 }
271 MaxTL << 8 |
272 (NWindows -1) << 0;
273
274 case MISCREG_STRAND_STS_REG:
275 System *sys;
276 int x;
277 sys = tc->getSystemPtr();
278

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329 assert(ticks >= 0 && "stick compare missed interrupt cycle");
330
331 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
332 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
333 (stick_cmpr & mask(63)));
334 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
335 setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
336 }
337 } else
337 } else {
338 cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1));
338 cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1));
339 }
339}
340
341void
342ISA::processHSTickCompare(ThreadContext *tc)
343{
344 BaseCPU *cpu = tc->getCpuPtr();
345
346 // since our microcode instructions take two cycles we need to check if

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356
357 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
358 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
359 (stick_cmpr & mask(63)));
360 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
361 setMiscReg(MISCREG_HINTP, 1, tc);
362 }
363 // Need to do something to cause interrupt to happen here !!! @todo
340}
341
342void
343ISA::processHSTickCompare(ThreadContext *tc)
344{
345 BaseCPU *cpu = tc->getCpuPtr();
346
347 // since our microcode instructions take two cycles we need to check if

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357
358 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
359 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
360 (stick_cmpr & mask(63)));
361 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
362 setMiscReg(MISCREG_HINTP, 1, tc);
363 }
364 // Need to do something to cause interrupt to happen here !!! @todo
364 } else
365 } else {
365 cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1));
366 cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1));
367 }
366}
367
368}
369