ua2005.cc (5606:6da7a58b0bc8) ua2005.cc (5704:98224505352a)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39
40void
41MiscRegFile::checkSoftInt(ThreadContext *tc)
42{
43 BaseCPU *cpu = tc->getCpuPtr();
44
45 // If PIL < 14, copy over the tm and sm bits
46 if (pil < 14 && softint & 0x10000)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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39
40void
41MiscRegFile::checkSoftInt(ThreadContext *tc)
42{
43 BaseCPU *cpu = tc->getCpuPtr();
44
45 // If PIL < 14, copy over the tm and sm bits
46 if (pil < 14 && softint & 0x10000)
47 cpu->post_interrupt(IT_SOFT_INT, 16);
47 cpu->postInterrupt(IT_SOFT_INT, 16);
48 else
48 else
49 cpu->clear_interrupt(IT_SOFT_INT, 16);
49 cpu->clearInterrupt(IT_SOFT_INT, 16);
50 if (pil < 14 && softint & 0x1)
50 if (pil < 14 && softint & 0x1)
51 cpu->post_interrupt(IT_SOFT_INT, 0);
51 cpu->postInterrupt(IT_SOFT_INT, 0);
52 else
52 else
53 cpu->clear_interrupt(IT_SOFT_INT, 0);
53 cpu->clearInterrupt(IT_SOFT_INT, 0);
54
55 // Copy over any of the other bits that are set
56 for (int bit = 15; bit > 0; --bit) {
57 if (1 << bit & softint && bit > pil)
54
55 // Copy over any of the other bits that are set
56 for (int bit = 15; bit > 0; --bit) {
57 if (1 << bit & softint && bit > pil)
58 cpu->post_interrupt(IT_SOFT_INT, bit);
58 cpu->postInterrupt(IT_SOFT_INT, bit);
59 else
59 else
60 cpu->clear_interrupt(IT_SOFT_INT, bit);
60 cpu->clearInterrupt(IT_SOFT_INT, bit);
61 }
62}
63
64
65void
66MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
67{
68 BaseCPU *cpu = tc->getCpuPtr();

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119 break;
120
121 case MISCREG_HVER:
122 panic("Shouldn't be writing HVER\n");
123
124 case MISCREG_HINTP:
125 setRegNoEffect(miscReg, val);
126 if (hintp)
61 }
62}
63
64
65void
66MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
67{
68 BaseCPU *cpu = tc->getCpuPtr();

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119 break;
120
121 case MISCREG_HVER:
122 panic("Shouldn't be writing HVER\n");
123
124 case MISCREG_HINTP:
125 setRegNoEffect(miscReg, val);
126 if (hintp)
127 cpu->post_interrupt(IT_HINTP, 0);
127 cpu->postInterrupt(IT_HINTP, 0);
128 else
128 else
129 cpu->clear_interrupt(IT_HINTP, 0);
129 cpu->clearInterrupt(IT_HINTP, 0);
130 break;
131
132 case MISCREG_HTBA:
133 // clear lower 7 bits on writes.
134 setRegNoEffect(miscReg, val & ULL(~0x7FFF));
135 break;
136
137 case MISCREG_QUEUE_CPU_MONDO_HEAD:
138 case MISCREG_QUEUE_CPU_MONDO_TAIL:
139 setRegNoEffect(miscReg, val);
140 if (cpu_mondo_head != cpu_mondo_tail)
130 break;
131
132 case MISCREG_HTBA:
133 // clear lower 7 bits on writes.
134 setRegNoEffect(miscReg, val & ULL(~0x7FFF));
135 break;
136
137 case MISCREG_QUEUE_CPU_MONDO_HEAD:
138 case MISCREG_QUEUE_CPU_MONDO_TAIL:
139 setRegNoEffect(miscReg, val);
140 if (cpu_mondo_head != cpu_mondo_tail)
141 cpu->post_interrupt(IT_CPU_MONDO, 0);
141 cpu->postInterrupt(IT_CPU_MONDO, 0);
142 else
142 else
143 cpu->clear_interrupt(IT_CPU_MONDO, 0);
143 cpu->clearInterrupt(IT_CPU_MONDO, 0);
144 break;
145 case MISCREG_QUEUE_DEV_MONDO_HEAD:
146 case MISCREG_QUEUE_DEV_MONDO_TAIL:
147 setRegNoEffect(miscReg, val);
148 if (dev_mondo_head != dev_mondo_tail)
144 break;
145 case MISCREG_QUEUE_DEV_MONDO_HEAD:
146 case MISCREG_QUEUE_DEV_MONDO_TAIL:
147 setRegNoEffect(miscReg, val);
148 if (dev_mondo_head != dev_mondo_tail)
149 cpu->post_interrupt(IT_DEV_MONDO, 0);
149 cpu->postInterrupt(IT_DEV_MONDO, 0);
150 else
150 else
151 cpu->clear_interrupt(IT_DEV_MONDO, 0);
151 cpu->clearInterrupt(IT_DEV_MONDO, 0);
152 break;
153 case MISCREG_QUEUE_RES_ERROR_HEAD:
154 case MISCREG_QUEUE_RES_ERROR_TAIL:
155 setRegNoEffect(miscReg, val);
156 if (res_error_head != res_error_tail)
152 break;
153 case MISCREG_QUEUE_RES_ERROR_HEAD:
154 case MISCREG_QUEUE_RES_ERROR_TAIL:
155 setRegNoEffect(miscReg, val);
156 if (res_error_head != res_error_tail)
157 cpu->post_interrupt(IT_RES_ERROR, 0);
157 cpu->postInterrupt(IT_RES_ERROR, 0);
158 else
158 else
159 cpu->clear_interrupt(IT_RES_ERROR, 0);
159 cpu->clearInterrupt(IT_RES_ERROR, 0);
160 break;
161 case MISCREG_QUEUE_NRES_ERROR_HEAD:
162 case MISCREG_QUEUE_NRES_ERROR_TAIL:
163 setRegNoEffect(miscReg, val);
164 // This one doesn't have an interrupt to report to the guest OS
165 break;
166
167 case MISCREG_HSTICK_CMPR:

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180 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
181 break;
182
183 case MISCREG_HPSTATE:
184 // T1000 spec says impl. dependent val must always be 1
185 setRegNoEffect(miscReg, val | HPSTATE::id);
186#if FULL_SYSTEM
187 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
160 break;
161 case MISCREG_QUEUE_NRES_ERROR_HEAD:
162 case MISCREG_QUEUE_NRES_ERROR_TAIL:
163 setRegNoEffect(miscReg, val);
164 // This one doesn't have an interrupt to report to the guest OS
165 break;
166
167 case MISCREG_HSTICK_CMPR:

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180 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
181 break;
182
183 case MISCREG_HPSTATE:
184 // T1000 spec says impl. dependent val must always be 1
185 setRegNoEffect(miscReg, val | HPSTATE::id);
186#if FULL_SYSTEM
187 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
188 cpu->post_interrupt(IT_TRAP_LEVEL_ZERO, 0);
188 cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
189 else
189 else
190 cpu->clear_interrupt(IT_TRAP_LEVEL_ZERO, 0);
190 cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
191#endif
192 break;
193 case MISCREG_HTSTATE:
194 setRegNoEffect(miscReg, val);
195 break;
196
197 case MISCREG_STRAND_STS_REG:
198 if (bits(val,2,2))

--- 148 unchanged lines hidden --- 		191#endif
192 break;
193 case MISCREG_HTSTATE:
194 setRegNoEffect(miscReg, val);
195 break;
196
197 case MISCREG_STRAND_STS_REG:
198 if (bits(val,2,2))

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