ua2005.cc (5531:a5ff5e57fafd) ua2005.cc (5606:6da7a58b0bc8)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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79 case MISCREG_SOFTINT_SET:
80 return setReg(MISCREG_SOFTINT, val | softint, tc);
81
82 case MISCREG_TICK_CMPR:
83 if (tickCompare == NULL)
84 tickCompare = new TickCompareEvent(this, tc);
85 setRegNoEffect(miscReg, val);
86 if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 70 unchanged lines hidden (view full) ---

79 case MISCREG_SOFTINT_SET:
80 return setReg(MISCREG_SOFTINT, val | softint, tc);
81
82 case MISCREG_TICK_CMPR:
83 if (tickCompare == NULL)
84 tickCompare = new TickCompareEvent(this, tc);
85 setRegNoEffect(miscReg, val);
86 if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
87 tickCompare->deschedule();
87 cpu->deschedule(tickCompare);
88 time = (tick_cmpr & mask(63)) - (tick & mask(63));
89 if (!(tick_cmpr & ~mask(63)) && time > 0) {
90 if (tickCompare->scheduled())
88 time = (tick_cmpr & mask(63)) - (tick & mask(63));
89 if (!(tick_cmpr & ~mask(63)) && time > 0) {
90 if (tickCompare->scheduled())
91 tickCompare->deschedule();
92 tickCompare->schedule(time * cpu->ticks(1));
91 cpu->deschedule(tickCompare);
92 cpu->schedule(tickCompare, curTick + time * cpu->ticks(1));
93 }
94 panic("writing to TICK compare register %#X\n", val);
95 break;
96
97 case MISCREG_STICK_CMPR:
98 if (sTickCompare == NULL)
99 sTickCompare = new STickCompareEvent(this, tc);
100 setRegNoEffect(miscReg, val);
101 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
93 }
94 panic("writing to TICK compare register %#X\n", val);
95 break;
96
97 case MISCREG_STICK_CMPR:
98 if (sTickCompare == NULL)
99 sTickCompare = new STickCompareEvent(this, tc);
100 setRegNoEffect(miscReg, val);
101 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
102 sTickCompare->deschedule();
102 cpu->deschedule(sTickCompare);
103 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
104 cpu->instCount();
105 if (!(stick_cmpr & ~mask(63)) && time > 0) {
106 if (sTickCompare->scheduled())
103 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
104 cpu->instCount();
105 if (!(stick_cmpr & ~mask(63)) && time > 0) {
106 if (sTickCompare->scheduled())
107 sTickCompare->deschedule();
108 sTickCompare->schedule(time * cpu->ticks(1) + curTick);
107 cpu->deschedule(sTickCompare);
108 cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1));
109 }
110 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
111 break;
112
113 case MISCREG_PSTATE:
114 setRegNoEffect(miscReg, val);
115
116 case MISCREG_PIL:

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164 // This one doesn't have an interrupt to report to the guest OS
165 break;
166
167 case MISCREG_HSTICK_CMPR:
168 if (hSTickCompare == NULL)
169 hSTickCompare = new HSTickCompareEvent(this, tc);
170 setRegNoEffect(miscReg, val);
171 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
109 }
110 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
111 break;
112
113 case MISCREG_PSTATE:
114 setRegNoEffect(miscReg, val);
115
116 case MISCREG_PIL:

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164 // This one doesn't have an interrupt to report to the guest OS
165 break;
166
167 case MISCREG_HSTICK_CMPR:
168 if (hSTickCompare == NULL)
169 hSTickCompare = new HSTickCompareEvent(this, tc);
170 setRegNoEffect(miscReg, val);
171 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
172 hSTickCompare->deschedule();
172 cpu->deschedule(hSTickCompare);
173 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
174 cpu->instCount();
175 if (!(hstick_cmpr & ~mask(63)) && time > 0) {
176 if (hSTickCompare->scheduled())
173 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
174 cpu->instCount();
175 if (!(hstick_cmpr & ~mask(63)) && time > 0) {
176 if (hSTickCompare->scheduled())
177 hSTickCompare->deschedule();
178 hSTickCompare->schedule(curTick + time * cpu->ticks(1));
177 cpu->deschedule(hSTickCompare);
178 cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1));
179 }
180 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
181 break;
182
183 case MISCREG_HPSTATE:
184 // T1000 spec says impl. dependent val must always be 1
185 setRegNoEffect(miscReg, val | HPSTATE::id);
186#if FULL_SYSTEM

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291MiscRegFile::processTickCompare(ThreadContext *tc)
292{
293 panic("tick compare not implemented\n");
294}
295
296void
297MiscRegFile::processSTickCompare(ThreadContext *tc)
298{
179 }
180 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
181 break;
182
183 case MISCREG_HPSTATE:
184 // T1000 spec says impl. dependent val must always be 1
185 setRegNoEffect(miscReg, val | HPSTATE::id);
186#if FULL_SYSTEM

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291MiscRegFile::processTickCompare(ThreadContext *tc)
292{
293 panic("tick compare not implemented\n");
294}
295
296void
297MiscRegFile::processSTickCompare(ThreadContext *tc)
298{
299 BaseCPU *cpu = tc->getCpuPtr();
300
299 // since our microcode instructions take two cycles we need to check if
300 // we're actually at the correct cycle or we need to wait a little while
301 // more
302 int ticks;
303 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
301 // since our microcode instructions take two cycles we need to check if
302 // we're actually at the correct cycle or we need to wait a little while
303 // more
304 int ticks;
305 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
304 tc->getCpuPtr()->instCount();
306 cpu->instCount();
305 assert(ticks >= 0 && "stick compare missed interrupt cycle");
306
307 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
308 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
309 (stick_cmpr & mask(63)));
310 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
311 setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
312 }
313 } else
307 assert(ticks >= 0 && "stick compare missed interrupt cycle");
308
309 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
310 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
311 (stick_cmpr & mask(63)));
312 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
313 setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
314 }
315 } else
314 sTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
316 cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1));
315}
316
317void
318MiscRegFile::processHSTickCompare(ThreadContext *tc)
319{
317}
318
319void
320MiscRegFile::processHSTickCompare(ThreadContext *tc)
321{
322 BaseCPU *cpu = tc->getCpuPtr();
323
320 // since our microcode instructions take two cycles we need to check if
321 // we're actually at the correct cycle or we need to wait a little while
322 // more
323 int ticks;
324 if ( tc->status() == ThreadContext::Halted ||
325 tc->status() == ThreadContext::Unallocated)
326 return;
327
328 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
324 // since our microcode instructions take two cycles we need to check if
325 // we're actually at the correct cycle or we need to wait a little while
326 // more
327 int ticks;
328 if ( tc->status() == ThreadContext::Halted ||
329 tc->status() == ThreadContext::Unallocated)
330 return;
331
332 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
329 tc->getCpuPtr()->instCount();
333 cpu->instCount();
330 assert(ticks >= 0 && "hstick compare missed interrupt cycle");
331
332 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
333 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
334 (stick_cmpr & mask(63)));
335 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
336 setReg(MISCREG_HINTP, 1, tc);
337 }
338 // Need to do something to cause interrupt to happen here !!! @todo
339 } else
334 assert(ticks >= 0 && "hstick compare missed interrupt cycle");
335
336 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
337 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
338 (stick_cmpr & mask(63)));
339 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
340 setReg(MISCREG_HINTP, 1, tc);
341 }
342 // Need to do something to cause interrupt to happen here !!! @todo
343 } else
340 hSTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick);
344 cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1));
341}
342
345}
346