ua2005.cc (4216:c01745179a1f) | ua2005.cc (5100:7a0180040755) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 71 unchanged lines hidden (view full) --- 80 tickCompare = new TickCompareEvent(this, tc); 81 setRegNoEffect(miscReg, val); 82 if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 83 tickCompare->deschedule(); 84 time = (tick_cmpr & mask(63)) - (tick & mask(63)); 85 if (!(tick_cmpr & ~mask(63)) && time > 0) { 86 if (tickCompare->scheduled()) 87 tickCompare->deschedule(); | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 71 unchanged lines hidden (view full) --- 80 tickCompare = new TickCompareEvent(this, tc); 81 setRegNoEffect(miscReg, val); 82 if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 83 tickCompare->deschedule(); 84 time = (tick_cmpr & mask(63)) - (tick & mask(63)); 85 if (!(tick_cmpr & ~mask(63)) && time > 0) { 86 if (tickCompare->scheduled()) 87 tickCompare->deschedule(); |
88 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); | 88 tickCompare->schedule(time * tc->getCpuPtr()->ticks(1)); |
89 } 90 panic("writing to TICK compare register %#X\n", val); 91 break; 92 93 case MISCREG_STICK_CMPR: 94 if (sTickCompare == NULL) 95 sTickCompare = new STickCompareEvent(this, tc); 96 setRegNoEffect(miscReg, val); 97 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 98 sTickCompare->deschedule(); 99 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 100 tc->getCpuPtr()->instCount(); 101 if (!(stick_cmpr & ~mask(63)) && time > 0) { 102 if (sTickCompare->scheduled()) 103 sTickCompare->deschedule(); | 89 } 90 panic("writing to TICK compare register %#X\n", val); 91 break; 92 93 case MISCREG_STICK_CMPR: 94 if (sTickCompare == NULL) 95 sTickCompare = new STickCompareEvent(this, tc); 96 setRegNoEffect(miscReg, val); 97 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 98 sTickCompare->deschedule(); 99 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 100 tc->getCpuPtr()->instCount(); 101 if (!(stick_cmpr & ~mask(63)) && time > 0) { 102 if (sTickCompare->scheduled()) 103 sTickCompare->deschedule(); |
104 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick); | 104 sTickCompare->schedule(time * tc->getCpuPtr()->ticks(1) + curTick); |
105 } 106 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 107 break; 108 109 case MISCREG_PSTATE: 110 setRegNoEffect(miscReg, val); 111 112 case MISCREG_PIL: --- 53 unchanged lines hidden (view full) --- 166 setRegNoEffect(miscReg, val); 167 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 168 hSTickCompare->deschedule(); 169 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 170 tc->getCpuPtr()->instCount(); 171 if (!(hstick_cmpr & ~mask(63)) && time > 0) { 172 if (hSTickCompare->scheduled()) 173 hSTickCompare->deschedule(); | 105 } 106 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 107 break; 108 109 case MISCREG_PSTATE: 110 setRegNoEffect(miscReg, val); 111 112 case MISCREG_PIL: --- 53 unchanged lines hidden (view full) --- 166 setRegNoEffect(miscReg, val); 167 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 168 hSTickCompare->deschedule(); 169 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 170 tc->getCpuPtr()->instCount(); 171 if (!(hstick_cmpr & ~mask(63)) && time > 0) { 172 if (hSTickCompare->scheduled()) 173 hSTickCompare->deschedule(); |
174 hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1)); | 174 hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->ticks(1)); |
175 } 176 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 177 break; 178 179 case MISCREG_HPSTATE: 180 // T1000 spec says impl. dependent val must always be 1 181 setRegNoEffect(miscReg, val | HPSTATE::id); 182#if FULL_SYSTEM --- 127 unchanged lines hidden (view full) --- 310 311 if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 312 DPRINTF(Timer, "STick compare cycle reached at %#x\n", 313 (stick_cmpr & mask(63))); 314 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 315 setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 316 } 317 } else | 175 } 176 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 177 break; 178 179 case MISCREG_HPSTATE: 180 // T1000 spec says impl. dependent val must always be 1 181 setRegNoEffect(miscReg, val | HPSTATE::id); 182#if FULL_SYSTEM --- 127 unchanged lines hidden (view full) --- 310 311 if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 312 DPRINTF(Timer, "STick compare cycle reached at %#x\n", 313 (stick_cmpr & mask(63))); 314 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 315 setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 316 } 317 } else |
318 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); | 318 sTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick); |
319} 320 321void 322MiscRegFile::processHSTickCompare(ThreadContext *tc) 323{ 324 // since our microcode instructions take two cycles we need to check if 325 // we're actually at the correct cycle or we need to wait a little while 326 // more --- 9 unchanged lines hidden (view full) --- 336 if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 337 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 338 (stick_cmpr & mask(63))); 339 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 340 setReg(MISCREG_HINTP, 1, tc); 341 } 342 // Need to do something to cause interrupt to happen here !!! @todo 343 } else | 319} 320 321void 322MiscRegFile::processHSTickCompare(ThreadContext *tc) 323{ 324 // since our microcode instructions take two cycles we need to check if 325 // we're actually at the correct cycle or we need to wait a little while 326 // more --- 9 unchanged lines hidden (view full) --- 336 if (ticks == 0 || tc->status() == ThreadContext::Suspended) { 337 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 338 (stick_cmpr & mask(63))); 339 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 340 setReg(MISCREG_HINTP, 1, tc); 341 } 342 // Need to do something to cause interrupt to happen here !!! @todo 343 } else |
344 hSTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); | 344 hSTickCompare->schedule(ticks * tc->getCpuPtr()->ticks(1) + curTick); |
345} 346 | 345} 346 |