ua2005.cc (4185:42c0395a03f9) ua2005.cc (4194:af4f6022394b)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 12 unchanged lines hidden (view full) ---

21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/sparc/kernel_stats.hh"
29#include "arch/sparc/miscregfile.hh"
30#include "base/bitfield.hh"
31#include "base/trace.hh"
32#include "cpu/base.hh"
33#include "cpu/thread_context.hh"
30#include "arch/sparc/miscregfile.hh"
31#include "base/bitfield.hh"
32#include "base/trace.hh"
33#include "cpu/base.hh"
34#include "cpu/thread_context.hh"
35#include "sim/system.hh"
34
35using namespace SparcISA;
36
37
38void
39MiscRegFile::checkSoftInt(ThreadContext *tc)
40{
41 // If PIL < 14, copy over the tm and sm bits

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180#if FULL_SYSTEM
181 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
182 tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
183 else
184 tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0);
185#endif
186 break;
187 case MISCREG_HTSTATE:
36
37using namespace SparcISA;
38
39
40void
41MiscRegFile::checkSoftInt(ThreadContext *tc)
42{
43 // If PIL < 14, copy over the tm and sm bits

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182#if FULL_SYSTEM
183 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
184 tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
185 else
186 tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0);
187#endif
188 break;
189 case MISCREG_HTSTATE:
188 case MISCREG_STRAND_STS_REG:
189 setRegNoEffect(miscReg, val);
190 break;
191
190 setRegNoEffect(miscReg, val);
191 break;
192
193 case MISCREG_STRAND_STS_REG:
194 if (bits(val,2,2))
195 panic("No support for setting spec_en bit\n");
196 setRegNoEffect(miscReg, bits(val,0,0));
197 if (!bits(val,0,0)) {
198 // Time to go to sleep
199 tc->suspend();
200 if (tc->getKernelStats())
201 tc->getKernelStats()->quiesce();
202 }
203 break;
204
192 default:
193 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
194 }
195}
196
197MiscReg
198MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
199{
205 default:
206 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
207 }
208}
209
210MiscReg
211MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
212{
213 uint64_t temp;
214
200 switch (miscReg) {
201 /* Privileged registers. */
202 case MISCREG_QUEUE_CPU_MONDO_HEAD:
203 case MISCREG_QUEUE_CPU_MONDO_TAIL:
204 case MISCREG_QUEUE_DEV_MONDO_HEAD:
205 case MISCREG_QUEUE_DEV_MONDO_TAIL:
206 case MISCREG_QUEUE_RES_ERROR_HEAD:
207 case MISCREG_QUEUE_RES_ERROR_TAIL:
208 case MISCREG_QUEUE_NRES_ERROR_HEAD:
209 case MISCREG_QUEUE_NRES_ERROR_TAIL:
210 case MISCREG_SOFTINT:
211 case MISCREG_TICK_CMPR:
212 case MISCREG_STICK_CMPR:
213 case MISCREG_PIL:
214 case MISCREG_HPSTATE:
215 case MISCREG_HINTP:
216 case MISCREG_HTSTATE:
215 switch (miscReg) {
216 /* Privileged registers. */
217 case MISCREG_QUEUE_CPU_MONDO_HEAD:
218 case MISCREG_QUEUE_CPU_MONDO_TAIL:
219 case MISCREG_QUEUE_DEV_MONDO_HEAD:
220 case MISCREG_QUEUE_DEV_MONDO_TAIL:
221 case MISCREG_QUEUE_RES_ERROR_HEAD:
222 case MISCREG_QUEUE_RES_ERROR_TAIL:
223 case MISCREG_QUEUE_NRES_ERROR_HEAD:
224 case MISCREG_QUEUE_NRES_ERROR_TAIL:
225 case MISCREG_SOFTINT:
226 case MISCREG_TICK_CMPR:
227 case MISCREG_STICK_CMPR:
228 case MISCREG_PIL:
229 case MISCREG_HPSTATE:
230 case MISCREG_HINTP:
231 case MISCREG_HTSTATE:
217 case MISCREG_STRAND_STS_REG:
218 case MISCREG_HSTICK_CMPR:
219 return readRegNoEffect(miscReg) ;
220
221 case MISCREG_HTBA:
222 return readRegNoEffect(miscReg) & ULL(~0x7FFF);
223 case MISCREG_HVER:
224 return NWindows | MaxTL << 8 | MaxGL << 16;
225
232 case MISCREG_HSTICK_CMPR:
233 return readRegNoEffect(miscReg) ;
234
235 case MISCREG_HTBA:
236 return readRegNoEffect(miscReg) & ULL(~0x7FFF);
237 case MISCREG_HVER:
238 return NWindows | MaxTL << 8 | MaxGL << 16;
239
240 case MISCREG_STRAND_STS_REG:
241 System *sys;
242 int x;
243 sys = tc->getSystemPtr();
244
245 temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
246 // Check that the CPU array is fully populated (by calling getNumCPus())
247 assert(sys->getNumCPUs() > tc->readCpuId());
248
249 temp |= tc->readCpuId() << STS::shft_id;
250
251 for (x = tc->readCpuId() & ~3; x < sys->threadContexts.size(); x++) {
252 switch (sys->threadContexts[x]->status()) {
253 case ThreadContext::Active:
254 temp |= STS::st_run << (STS::shft_fsm0 -
255 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
256 break;
257 case ThreadContext::Suspended:
258 // should this be idle?
259 temp |= STS::st_idle << (STS::shft_fsm0 -
260 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
261 break;
262 case ThreadContext::Halted:
263 temp |= STS::st_halt << (STS::shft_fsm0 -
264 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
265 break;
266 default:
267 panic("What state are we in?!\n");
268 } // switch
269 } // for
270
271 return temp;
226 default:
227 panic("Invalid read to FS misc register\n");
228 }
229}
230/*
231 In Niagra STICK==TICK so this isn't needed
232 case MISCREG_STICK:
233 SparcSystem *sys;

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273 panic("Invalid read to FS misc register\n");
274 }
275}
276/*
277 In Niagra STICK==TICK so this isn't needed
278 case MISCREG_STICK:
279 SparcSystem *sys;

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