ua2005.cc (4172:141705d83494) ua2005.cc (4185:42c0395a03f9)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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54 tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,bit);
55 else
56 tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,bit);
57 }
58}
59
60
61void
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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54 tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,bit);
55 else
56 tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,bit);
57 }
58}
59
60
61void
62MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
63 ThreadContext *tc)
62MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
64{
65 int64_t time;
66 switch (miscReg) {
67 /* Full system only ASRs */
68 case MISCREG_SOFTINT:
69 setRegNoEffect(miscReg, val);;
70 checkSoftInt(tc);
71 break;

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191 break;
192
193 default:
194 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
195 }
196}
197
198MiscReg
63{
64 int64_t time;
65 switch (miscReg) {
66 /* Full system only ASRs */
67 case MISCREG_SOFTINT:
68 setRegNoEffect(miscReg, val);;
69 checkSoftInt(tc);
70 break;

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190 break;
191
192 default:
193 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
194 }
195}
196
197MiscReg
199MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
198MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
200{
201 switch (miscReg) {
202 /* Privileged registers. */
203 case MISCREG_QUEUE_CPU_MONDO_HEAD:
204 case MISCREG_QUEUE_CPU_MONDO_TAIL:
205 case MISCREG_QUEUE_DEV_MONDO_HEAD:
206 case MISCREG_QUEUE_DEV_MONDO_TAIL:
207 case MISCREG_QUEUE_RES_ERROR_HEAD:

--- 83 unchanged lines hidden --- 		199{
200 switch (miscReg) {
201 /* Privileged registers. */
202 case MISCREG_QUEUE_CPU_MONDO_HEAD:
203 case MISCREG_QUEUE_CPU_MONDO_TAIL:
204 case MISCREG_QUEUE_DEV_MONDO_HEAD:
205 case MISCREG_QUEUE_DEV_MONDO_TAIL:
206 case MISCREG_QUEUE_RES_ERROR_HEAD:

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