ua2005.cc (3828:9444f62adb12) ua2005.cc (3831:2a4e8de75870)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 113 unchanged lines hidden (view full) ---

122 if (!(hstick_cmpr & ~mask(63)) && time > 0)
123 hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
124 warn ("writing to hsTICK compare register value %#X\n", val);
125 break;
126
127 case MISCREG_HPSTATE:
128 // T1000 spec says impl. dependent val must always be 1
129 setReg(miscReg, val | id);
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 113 unchanged lines hidden (view full) ---

122 if (!(hstick_cmpr & ~mask(63)) && time > 0)
123 hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
124 warn ("writing to hsTICK compare register value %#X\n", val);
125 break;
126
127 case MISCREG_HPSTATE:
128 // T1000 spec says impl. dependent val must always be 1
129 setReg(miscReg, val | id);
130
130 break;
131 case MISCREG_HTSTATE:
132 case MISCREG_STRAND_STS_REG:
133 setReg(miscReg, val);
134 break;
135
136 default:
137 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
138 }

--- 64 unchanged lines hidden --- 		131 case MISCREG_HTSTATE:
132 case MISCREG_STRAND_STS_REG:
133 setReg(miscReg, val);
134 break;
135
136 default:
137 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
138 }

--- 64 unchanged lines hidden ---