ua2005.cc (3827:030cb88ad449) ua2005.cc (3828:9444f62adb12)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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42{
43 int64_t time;
44 switch (miscReg) {
45 /* Full system only ASRs */
46 case MISCREG_SOFTINT:
47 // Check if we are going to interrupt because of something
48 setReg(miscReg, val);
49 tc->getCpuPtr()->checkInterrupts = true;
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 33 unchanged lines hidden (view full) ---

42{
43 int64_t time;
44 switch (miscReg) {
45 /* Full system only ASRs */
46 case MISCREG_SOFTINT:
47 // Check if we are going to interrupt because of something
48 setReg(miscReg, val);
49 tc->getCpuPtr()->checkInterrupts = true;
50 warn("Writing to softint not really supported, writing: %#x\n", val);
50 break;
51
52 case MISCREG_SOFTINT_CLR:
53 return setRegWithEffect(miscReg, ~val & softint, tc);
54 case MISCREG_SOFTINT_SET:
55 return setRegWithEffect(miscReg, val | softint, tc);
56
57 case MISCREG_TICK_CMPR:
58 if (tickCompare == NULL)
59 tickCompare = new TickCompareEvent(this, tc);
60 setReg(miscReg, val);
61 if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
62 tickCompare->deschedule();
63 time = (tick_cmpr & mask(63)) - (tick & mask(63));
64 if (!(tick_cmpr & ~mask(63)) && time > 0)
65 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
51 break;
52
53 case MISCREG_SOFTINT_CLR:
54 return setRegWithEffect(miscReg, ~val & softint, tc);
55 case MISCREG_SOFTINT_SET:
56 return setRegWithEffect(miscReg, val | softint, tc);
57
58 case MISCREG_TICK_CMPR:
59 if (tickCompare == NULL)
60 tickCompare = new TickCompareEvent(this, tc);
61 setReg(miscReg, val);
62 if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
63 tickCompare->deschedule();
64 time = (tick_cmpr & mask(63)) - (tick & mask(63));
65 if (!(tick_cmpr & ~mask(63)) && time > 0)
66 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
67 warn ("writing to TICK compare register %#X\n", val);
66 break;
67
68 case MISCREG_STICK_CMPR:
69 if (sTickCompare == NULL)
70 sTickCompare = new STickCompareEvent(this, tc);
71 setReg(miscReg, val);
72 if ((stick_cmpr & mask(63)) && sTickCompare->scheduled())
73 sTickCompare->deschedule();
74 time = (stick_cmpr & mask(63)) - (stick & mask(63));
75 if (!(stick_cmpr & ~mask(63)) && time > 0)
76 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
68 break;
69
70 case MISCREG_STICK_CMPR:
71 if (sTickCompare == NULL)
72 sTickCompare = new STickCompareEvent(this, tc);
73 setReg(miscReg, val);
74 if ((stick_cmpr & mask(63)) && sTickCompare->scheduled())
75 sTickCompare->deschedule();
76 time = (stick_cmpr & mask(63)) - (stick & mask(63));
77 if (!(stick_cmpr & ~mask(63)) && time > 0)
78 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
79 warn ("writing to sTICK compare register value %#X\n", val);
77 break;
78
79 case MISCREG_PSTATE:
80 if (val & ie && !(pstate & ie)) {
81 tc->getCpuPtr()->checkInterrupts = true;
82 }
83 setReg(miscReg, val);
84

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92 case MISCREG_HVER:
93 panic("Shouldn't be writing HVER\n");
94
95 case MISCREG_HTBA:
96 // clear lower 7 bits on writes.
97 setReg(miscReg, val & ULL(~0x7FFF));
98 break;
99
80 break;
81
82 case MISCREG_PSTATE:
83 if (val & ie && !(pstate & ie)) {
84 tc->getCpuPtr()->checkInterrupts = true;
85 }
86 setReg(miscReg, val);
87

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95 case MISCREG_HVER:
96 panic("Shouldn't be writing HVER\n");
97
98 case MISCREG_HTBA:
99 // clear lower 7 bits on writes.
100 setReg(miscReg, val & ULL(~0x7FFF));
101 break;
102
103 case MISCREG_QUEUE_CPU_MONDO_HEAD:
104 case MISCREG_QUEUE_CPU_MONDO_TAIL:
105 case MISCREG_QUEUE_DEV_MONDO_HEAD:
106 case MISCREG_QUEUE_DEV_MONDO_TAIL:
107 case MISCREG_QUEUE_RES_ERROR_HEAD:
108 case MISCREG_QUEUE_RES_ERROR_TAIL:
109 case MISCREG_QUEUE_NRES_ERROR_HEAD:
110 case MISCREG_QUEUE_NRES_ERROR_TAIL:
111 setReg(miscReg, val);
112 tc->getCpuPtr()->checkInterrupts = true;
113 break;
114
100 case MISCREG_HSTICK_CMPR:
101 if (hSTickCompare == NULL)
102 hSTickCompare = new HSTickCompareEvent(this, tc);
103 setReg(miscReg, val);
104 if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled())
115 case MISCREG_HSTICK_CMPR:
116 if (hSTickCompare == NULL)
117 hSTickCompare = new HSTickCompareEvent(this, tc);
118 setReg(miscReg, val);
119 if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled())
105 hSTickCompare->deschedule();
120 hSTickCompare->deschedule();
106 time = (hstick_cmpr & mask(63)) - (stick & mask(63));
107 if (!(hstick_cmpr & ~mask(63)) && time > 0)
108 hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
121 time = (hstick_cmpr & mask(63)) - (stick & mask(63));
122 if (!(hstick_cmpr & ~mask(63)) && time > 0)
123 hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
124 warn ("writing to hsTICK compare register value %#X\n", val);
109 break;
110
111 case MISCREG_HPSTATE:
112 // T1000 spec says impl. dependent val must always be 1
113 setReg(miscReg, val | id);
114
115 case MISCREG_HTSTATE:
116 case MISCREG_STRAND_STS_REG:

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121 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
122 }
123}
124
125MiscReg
126MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
127{
128 switch (miscReg) {
125 break;
126
127 case MISCREG_HPSTATE:
128 // T1000 spec says impl. dependent val must always be 1
129 setReg(miscReg, val | id);
130
131 case MISCREG_HTSTATE:
132 case MISCREG_STRAND_STS_REG:

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137 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
138 }
139}
140
141MiscReg
142MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
143{
144 switch (miscReg) {
145 /* Privileged registers. */
146 case MISCREG_QUEUE_CPU_MONDO_HEAD:
147 case MISCREG_QUEUE_CPU_MONDO_TAIL:
148 case MISCREG_QUEUE_DEV_MONDO_HEAD:
149 case MISCREG_QUEUE_DEV_MONDO_TAIL:
150 case MISCREG_QUEUE_RES_ERROR_HEAD:
151 case MISCREG_QUEUE_RES_ERROR_TAIL:
152 case MISCREG_QUEUE_NRES_ERROR_HEAD:
153 case MISCREG_QUEUE_NRES_ERROR_TAIL:
154 case MISCREG_SOFTINT:
155 case MISCREG_TICK_CMPR:
156 case MISCREG_STICK_CMPR:
157 case MISCREG_PIL:
158 case MISCREG_HPSTATE:
159 case MISCREG_HINTP:
160 case MISCREG_HTSTATE:
161 case MISCREG_STRAND_STS_REG:
162 case MISCREG_HSTICK_CMPR:
163 return readReg(miscReg) ;
129
164
130 /* Privileged registers. */
131 case MISCREG_SOFTINT:
132 case MISCREG_TICK_CMPR:
133 case MISCREG_STICK_CMPR:
134 case MISCREG_PIL:
135 case MISCREG_HPSTATE:
136 case MISCREG_HINTP:
137 case MISCREG_HTSTATE:
138 case MISCREG_STRAND_STS_REG:
139 case MISCREG_HSTICK_CMPR:
140 return readReg(miscReg) ;
165 case MISCREG_HTBA:
166 return readReg(miscReg) & ULL(~0x7FFF);
167 case MISCREG_HVER:
168 return NWindows | MaxTL << 8 | MaxGL << 16;
141
169
142 case MISCREG_HTBA:
143 return readReg(miscReg) & ULL(~0x7FFF);
144 case MISCREG_HVER:
145 return NWindows | MaxTL << 8 | MaxGL << 16;
146
147 default:
148 panic("Invalid read to FS misc register\n");
170 default:
171 panic("Invalid read to FS misc register\n");
149 }
150}
151/*
152 In Niagra STICK==TICK so this isn't needed
153 case MISCREG_STICK:
154 SparcSystem *sys;
155 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
156 assert(sys != NULL);

--- 23 unchanged lines hidden --- 		172 }
173}
174/*
175 In Niagra STICK==TICK so this isn't needed
176 case MISCREG_STICK:
177 SparcSystem *sys;
178 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
179 assert(sys != NULL);

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