ua2005.cc (3825:9b5e6c4d3ecb) ua2005.cc (3827:030cb88ad449)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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36
37using namespace SparcISA;
38
39void
40MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
41 ThreadContext *tc)
42{
43 int64_t time;
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 27 unchanged lines hidden (view full) ---

36
37using namespace SparcISA;
38
39void
40MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
41 ThreadContext *tc)
42{
43 int64_t time;
44 int oldLevel, newLevel;
45 switch (miscReg) {
44 switch (miscReg) {
46 /* Full system only ASRs */
47 case MISCREG_SOFTINT:
48 // Check if we are going to interrupt because of something
49 oldLevel = InterruptLevel(softint);
50 newLevel = InterruptLevel(val);
51 setReg(miscReg, val);
52 //if (newLevel > oldLevel)
53 ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
54 //tc->getCpuPtr()->checkInterrupts = true;
55 //panic("SOFTINT not implemented\n");
56 warn("Writing to softint not really supported, writing: %#x\n", val);
57 break;
45 /* Full system only ASRs */
46 case MISCREG_SOFTINT:
47 // Check if we are going to interrupt because of something
48 setReg(miscReg, val);
49 tc->getCpuPtr()->checkInterrupts = true;
50 break;
58
51
59 case MISCREG_SOFTINT_CLR:
60 return setRegWithEffect(miscReg, ~val & softint, tc);
61 case MISCREG_SOFTINT_SET:
62 return setRegWithEffect(miscReg, val | softint, tc);
52 case MISCREG_SOFTINT_CLR:
53 return setRegWithEffect(miscReg, ~val & softint, tc);
54 case MISCREG_SOFTINT_SET:
55 return setRegWithEffect(miscReg, val | softint, tc);
63
56
64 case MISCREG_TICK_CMPR:
65 if (tickCompare == NULL)
66 tickCompare = new TickCompareEvent(this, tc);
67 setReg(miscReg, val);
68 if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
57 case MISCREG_TICK_CMPR:
58 if (tickCompare == NULL)
59 tickCompare = new TickCompareEvent(this, tc);
60 setReg(miscReg, val);
61 if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
69 tickCompare->deschedule();
62 tickCompare->deschedule();
70 time = (tick_cmpr & mask(63)) - (tick & mask(63));
71 if (!(tick_cmpr & ~mask(63)) && time > 0)
72 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
73 warn ("writing to TICK compare register %#X\n", val);
74 break;
63 time = (tick_cmpr & mask(63)) - (tick & mask(63));
64 if (!(tick_cmpr & ~mask(63)) && time > 0)
65 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
66 break;
75
67
76 case MISCREG_STICK_CMPR:
77 if (sTickCompare == NULL)
78 sTickCompare = new STickCompareEvent(this, tc);
79 setReg(miscReg, val);
80 if ((stick_cmpr & mask(63)) && sTickCompare->scheduled())
81 sTickCompare->deschedule();
82 time = (stick_cmpr & mask(63)) - (stick & mask(63));
83 if (!(stick_cmpr & ~mask(63)) && time > 0)
84 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
85 warn ("writing to sTICK compare register value %#X\n", val);
86 break;
68 case MISCREG_STICK_CMPR:
69 if (sTickCompare == NULL)
70 sTickCompare = new STickCompareEvent(this, tc);
71 setReg(miscReg, val);
72 if ((stick_cmpr & mask(63)) && sTickCompare->scheduled())
73 sTickCompare->deschedule();
74 time = (stick_cmpr & mask(63)) - (stick & mask(63));
75 if (!(stick_cmpr & ~mask(63)) && time > 0)
76 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
77 break;
87
78
88 case MISCREG_PIL:
89 setReg(miscReg, val);
90 //tc->getCpuPtr()->checkInterrupts;
91 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
92 // panic("PIL not implemented\n");
93 warn ("PIL not implemented writing %#X\n", val);
94 break;
79 case MISCREG_PSTATE:
80 if (val & ie && !(pstate & ie)) {
81 tc->getCpuPtr()->checkInterrupts = true;
82 }
83 setReg(miscReg, val);
95
84
96 case MISCREG_HVER:
97 panic("Shouldn't be writing HVER\n");
85 case MISCREG_PIL:
86 if (val < pil) {
87 tc->getCpuPtr()->checkInterrupts = true;
88 }
89 setReg(miscReg, val);
90 break;
98
91
99 case MISCREG_HTBA:
100 // clear lower 7 bits on writes.
101 setReg(miscReg, val & ULL(~0x7FFF));
102 break;
92 case MISCREG_HVER:
93 panic("Shouldn't be writing HVER\n");
103
94
104 case MISCREG_QUEUE_CPU_MONDO_HEAD:
105 case MISCREG_QUEUE_CPU_MONDO_TAIL:
106 case MISCREG_QUEUE_DEV_MONDO_HEAD:
107 case MISCREG_QUEUE_DEV_MONDO_TAIL:
108 case MISCREG_QUEUE_RES_ERROR_HEAD:
109 case MISCREG_QUEUE_RES_ERROR_TAIL:
110 case MISCREG_QUEUE_NRES_ERROR_HEAD:
111 case MISCREG_QUEUE_NRES_ERROR_TAIL:
112 setReg(miscReg, val);
113 tc->getCpuPtr()->checkInterrupts = true;
114 break;
95 case MISCREG_HTBA:
96 // clear lower 7 bits on writes.
97 setReg(miscReg, val & ULL(~0x7FFF));
98 break;
115
99
116 case MISCREG_HSTICK_CMPR:
117 if (hSTickCompare == NULL)
118 hSTickCompare = new HSTickCompareEvent(this, tc);
119 setReg(miscReg, val);
120 if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled())
121 hSTickCompare->deschedule();
122 time = (hstick_cmpr & mask(63)) - (stick & mask(63));
123 if (!(hstick_cmpr & ~mask(63)) && time > 0)
124 hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
125 warn ("writing to hsTICK compare register value %#X\n", val);
126 break;
100 case MISCREG_HSTICK_CMPR:
101 if (hSTickCompare == NULL)
102 hSTickCompare = new HSTickCompareEvent(this, tc);
103 setReg(miscReg, val);
104 if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled())
105 hSTickCompare->deschedule();
106 time = (hstick_cmpr & mask(63)) - (stick & mask(63));
107 if (!(hstick_cmpr & ~mask(63)) && time > 0)
108 hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
109 break;
127
110
128 case MISCREG_HPSTATE:
129 // i.d. is always set on any hpstate write
130 setReg(miscReg, val | 1 << 11);
131 break;
132 case MISCREG_HTSTATE:
133 case MISCREG_STRAND_STS_REG:
134 setReg(miscReg, val);
135 break;
111 case MISCREG_HPSTATE:
112 // T1000 spec says impl. dependent val must always be 1
113 setReg(miscReg, val | id);
136
114
137 default:
138 panic("Invalid write to FS misc register\n");
115 case MISCREG_HTSTATE:
116 case MISCREG_STRAND_STS_REG:
117 setReg(miscReg, val);
118 break;
119
120 default:
121 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
139 }
140}
141
142MiscReg
143MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
144{
145 switch (miscReg) {
122 }
123}
124
125MiscReg
126MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
127{
128 switch (miscReg) {
146 /* Privileged registers. */
147 case MISCREG_QUEUE_CPU_MONDO_HEAD:
148 case MISCREG_QUEUE_CPU_MONDO_TAIL:
149 case MISCREG_QUEUE_DEV_MONDO_HEAD:
150 case MISCREG_QUEUE_DEV_MONDO_TAIL:
151 case MISCREG_QUEUE_RES_ERROR_HEAD:
152 case MISCREG_QUEUE_RES_ERROR_TAIL:
153 case MISCREG_QUEUE_NRES_ERROR_HEAD:
154 case MISCREG_QUEUE_NRES_ERROR_TAIL:
155 case MISCREG_SOFTINT:
156 case MISCREG_TICK_CMPR:
157 case MISCREG_STICK_CMPR:
158 case MISCREG_PIL:
159 case MISCREG_HPSTATE:
160 case MISCREG_HINTP:
161 case MISCREG_HTSTATE:
162 case MISCREG_STRAND_STS_REG:
163 case MISCREG_HSTICK_CMPR:
164 return readReg(miscReg) ;
165
129
166 case MISCREG_HTBA:
167 return readReg(miscReg) & ULL(~0x7FFF);
168 case MISCREG_HVER:
169 return NWindows | MaxTL << 8 | MaxGL << 16;
130 /* Privileged registers. */
131 case MISCREG_SOFTINT:
132 case MISCREG_TICK_CMPR:
133 case MISCREG_STICK_CMPR:
134 case MISCREG_PIL:
135 case MISCREG_HPSTATE:
136 case MISCREG_HINTP:
137 case MISCREG_HTSTATE:
138 case MISCREG_STRAND_STS_REG:
139 case MISCREG_HSTICK_CMPR:
140 return readReg(miscReg) ;
170
141
171 default:
172 panic("Invalid read to FS misc register\n");
142 case MISCREG_HTBA:
143 return readReg(miscReg) & ULL(~0x7FFF);
144 case MISCREG_HVER:
145 return NWindows | MaxTL << 8 | MaxGL << 16;
146
147 default:
148 panic("Invalid read to FS misc register\n");
173 }
174}
175/*
176 In Niagra STICK==TICK so this isn't needed
177 case MISCREG_STICK:
178 SparcSystem *sys;
179 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
180 assert(sys != NULL);

--- 23 unchanged lines hidden --- 		149 }
150}
151/*
152 In Niagra STICK==TICK so this isn't needed
153 case MISCREG_STICK:
154 SparcSystem *sys;
155 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
156 assert(sys != NULL);

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