ua2005.cc (3817:7df12d77afc2) | ua2005.cc (3825:9b5e6c4d3ecb) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38 39void 40MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 41 ThreadContext *tc) 42{ 43 int64_t time; 44 int oldLevel, newLevel; 45 switch (miscReg) { | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38 39void 40MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 41 ThreadContext *tc) 42{ 43 int64_t time; 44 int oldLevel, newLevel; 45 switch (miscReg) { |
46 /* Full system only ASRs */ 47 case MISCREG_SOFTINT: 48 // Check if we are going to interrupt because of something 49 oldLevel = InterruptLevel(softint); 50 newLevel = InterruptLevel(val); 51 setReg(miscReg, val); 52 if (newLevel > oldLevel) 53 ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 54 //tc->getCpuPtr()->checkInterrupts = true; 55 panic("SOFTINT not implemented\n"); 56 break; | 46 /* Full system only ASRs */ 47 case MISCREG_SOFTINT: 48 // Check if we are going to interrupt because of something 49 oldLevel = InterruptLevel(softint); 50 newLevel = InterruptLevel(val); 51 setReg(miscReg, val); 52 //if (newLevel > oldLevel) 53 ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 54 //tc->getCpuPtr()->checkInterrupts = true; 55 //panic("SOFTINT not implemented\n"); 56 warn("Writing to softint not really supported, writing: %#x\n", val); 57 break; |
57 | 58 |
58 case MISCREG_SOFTINT_CLR: 59 return setRegWithEffect(miscReg, ~val & softint, tc); 60 case MISCREG_SOFTINT_SET: 61 return setRegWithEffect(miscReg, val | softint, tc); | 59 case MISCREG_SOFTINT_CLR: 60 return setRegWithEffect(miscReg, ~val & softint, tc); 61 case MISCREG_SOFTINT_SET: 62 return setRegWithEffect(miscReg, val | softint, tc); |
62 | 63 |
63 case MISCREG_TICK_CMPR: 64 if (tickCompare == NULL) 65 tickCompare = new TickCompareEvent(this, tc); 66 setReg(miscReg, val); 67 if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) | 64 case MISCREG_TICK_CMPR: 65 if (tickCompare == NULL) 66 tickCompare = new TickCompareEvent(this, tc); 67 setReg(miscReg, val); 68 if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) |
68 tickCompare->deschedule(); | 69 tickCompare->deschedule(); |
69 time = (tick_cmpr & mask(63)) - (tick & mask(63)); 70 if (!(tick_cmpr & ~mask(63)) && time > 0) 71 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 72 break; | 70 time = (tick_cmpr & mask(63)) - (tick & mask(63)); 71 if (!(tick_cmpr & ~mask(63)) && time > 0) 72 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 73 warn ("writing to TICK compare register %#X\n", val); 74 break; |
73 | 75 |
74 case MISCREG_STICK_CMPR: 75 if (sTickCompare == NULL) 76 sTickCompare = new STickCompareEvent(this, tc); 77 setReg(miscReg, val); 78 if ((stick_cmpr & mask(63)) && sTickCompare->scheduled()) 79 sTickCompare->deschedule(); 80 time = (stick_cmpr & mask(63)) - (stick & mask(63)); 81 if (!(stick_cmpr & ~mask(63)) && time > 0) 82 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 83 break; | 76 case MISCREG_STICK_CMPR: 77 if (sTickCompare == NULL) 78 sTickCompare = new STickCompareEvent(this, tc); 79 setReg(miscReg, val); 80 if ((stick_cmpr & mask(63)) && sTickCompare->scheduled()) 81 sTickCompare->deschedule(); 82 time = (stick_cmpr & mask(63)) - (stick & mask(63)); 83 if (!(stick_cmpr & ~mask(63)) && time > 0) 84 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 85 warn ("writing to sTICK compare register value %#X\n", val); 86 break; |
84 | 87 |
85 case MISCREG_PIL: 86 setReg(miscReg, val); 87 //tc->getCpuPtr()->checkInterrupts; 88 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 89 panic("PIL not implemented\n"); 90 break; | 88 case MISCREG_PIL: 89 setReg(miscReg, val); 90 //tc->getCpuPtr()->checkInterrupts; 91 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 92 // panic("PIL not implemented\n"); 93 warn ("PIL not implemented writing %#X\n", val); 94 break; |
91 | 95 |
92 case MISCREG_HVER: 93 panic("Shouldn't be writing HVER\n"); | 96 case MISCREG_HVER: 97 panic("Shouldn't be writing HVER\n"); |
94 | 98 |
95 case MISCREG_HTBA: 96 // clear lower 7 bits on writes. 97 setReg(miscReg, val & ULL(~0x7FFF)); 98 break; | 99 case MISCREG_HTBA: 100 // clear lower 7 bits on writes. 101 setReg(miscReg, val & ULL(~0x7FFF)); 102 break; |
99 | 103 |
100 case MISCREG_HSTICK_CMPR: 101 if (hSTickCompare == NULL) 102 hSTickCompare = new HSTickCompareEvent(this, tc); 103 setReg(miscReg, val); 104 if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled()) 105 hSTickCompare->deschedule(); 106 time = (hstick_cmpr & mask(63)) - (stick & mask(63)); 107 if (!(hstick_cmpr & ~mask(63)) && time > 0) 108 hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 109 break; | 104 case MISCREG_QUEUE_CPU_MONDO_HEAD: 105 case MISCREG_QUEUE_CPU_MONDO_TAIL: 106 case MISCREG_QUEUE_DEV_MONDO_HEAD: 107 case MISCREG_QUEUE_DEV_MONDO_TAIL: 108 case MISCREG_QUEUE_RES_ERROR_HEAD: 109 case MISCREG_QUEUE_RES_ERROR_TAIL: 110 case MISCREG_QUEUE_NRES_ERROR_HEAD: 111 case MISCREG_QUEUE_NRES_ERROR_TAIL: 112 setReg(miscReg, val); 113 tc->getCpuPtr()->checkInterrupts = true; 114 break; |
110 | 115 |
111 case MISCREG_HPSTATE: 112 case MISCREG_HTSTATE: 113 case MISCREG_STRAND_STS_REG: 114 setReg(miscReg, val); 115 break; | 116 case MISCREG_HSTICK_CMPR: 117 if (hSTickCompare == NULL) 118 hSTickCompare = new HSTickCompareEvent(this, tc); 119 setReg(miscReg, val); 120 if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled()) 121 hSTickCompare->deschedule(); 122 time = (hstick_cmpr & mask(63)) - (stick & mask(63)); 123 if (!(hstick_cmpr & ~mask(63)) && time > 0) 124 hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 125 warn ("writing to hsTICK compare register value %#X\n", val); 126 break; |
116 | 127 |
117 default: 118 panic("Invalid write to FS misc register\n"); | 128 case MISCREG_HPSTATE: 129 // i.d. is always set on any hpstate write 130 setReg(miscReg, val | 1 << 11); 131 break; 132 case MISCREG_HTSTATE: 133 case MISCREG_STRAND_STS_REG: 134 setReg(miscReg, val); 135 break; 136 137 default: 138 panic("Invalid write to FS misc register\n"); |
119 } 120} 121 122MiscReg 123MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) 124{ 125 switch (miscReg) { | 139 } 140} 141 142MiscReg 143MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc) 144{ 145 switch (miscReg) { |
146 /* Privileged registers. */ 147 case MISCREG_QUEUE_CPU_MONDO_HEAD: 148 case MISCREG_QUEUE_CPU_MONDO_TAIL: 149 case MISCREG_QUEUE_DEV_MONDO_HEAD: 150 case MISCREG_QUEUE_DEV_MONDO_TAIL: 151 case MISCREG_QUEUE_RES_ERROR_HEAD: 152 case MISCREG_QUEUE_RES_ERROR_TAIL: 153 case MISCREG_QUEUE_NRES_ERROR_HEAD: 154 case MISCREG_QUEUE_NRES_ERROR_TAIL: 155 case MISCREG_SOFTINT: 156 case MISCREG_TICK_CMPR: 157 case MISCREG_STICK_CMPR: 158 case MISCREG_PIL: 159 case MISCREG_HPSTATE: 160 case MISCREG_HINTP: 161 case MISCREG_HTSTATE: 162 case MISCREG_STRAND_STS_REG: 163 case MISCREG_HSTICK_CMPR: 164 return readReg(miscReg) ; |
|
126 | 165 |
127 /* Privileged registers. */ 128 case MISCREG_SOFTINT: 129 case MISCREG_TICK_CMPR: 130 case MISCREG_STICK_CMPR: 131 case MISCREG_PIL: 132 case MISCREG_HPSTATE: 133 case MISCREG_HINTP: 134 case MISCREG_HTSTATE: 135 case MISCREG_STRAND_STS_REG: 136 case MISCREG_HSTICK_CMPR: 137 return readReg(miscReg) ; | 166 case MISCREG_HTBA: 167 return readReg(miscReg) & ULL(~0x7FFF); 168 case MISCREG_HVER: 169 return NWindows | MaxTL << 8 | MaxGL << 16; |
138 | 170 |
139 case MISCREG_HTBA: 140 return readReg(miscReg) & ULL(~0x7FFF); 141 case MISCREG_HVER: 142 return NWindows | MaxTL << 8 | MaxGL << 16; 143 144 default: 145 panic("Invalid read to FS misc register\n"); | 171 default: 172 panic("Invalid read to FS misc register\n"); |
146 } 147} 148/* 149 In Niagra STICK==TICK so this isn't needed 150 case MISCREG_STICK: 151 SparcSystem *sys; 152 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 153 assert(sys != NULL); --- 23 unchanged lines hidden --- | 173 } 174} 175/* 176 In Niagra STICK==TICK so this isn't needed 177 case MISCREG_STICK: 178 SparcSystem *sys; 179 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 180 assert(sys != NULL); --- 23 unchanged lines hidden --- |