Cross Reference: /gem5/src/arch/sparc/ua2005.cc

1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/regfile.hh"
32
33Fault
34SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,

35 ExecContext *xc)

35 ThreadContext *tc)

36{
37 int64_t time;
38 SparcSystem *sys;
39 switch (miscReg) {
40 /** Full system only ASRs */
41 case MISCREG_SOFTINT:
42 if (isNonPriv())
43 return new PrivilegedOpcode;
44 // Check if we are going to interrupt because of something
45 int oldLevel = InterruptLevel(softint);
46 int newLevel = InterruptLevel(val);
47 setReg(miscReg, val);
48 if (newLevel > oldLevel)
49 ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX

50 //xc->getCpuPtr()->checkInterrupts = true;

50 //tc->getCpuPtr()->checkInterrupts = true;

51 return NoFault;
52
53 case MISCREG_SOFTINT_CLR:

54 return setRegWithEffect(miscReg, ~val & softint, xc);

54 return setRegWithEffect(miscReg, ~val & softint, tc);

55 case MISCREG_SOFTINT_SET:

56 return setRegWithEffect(miscReg, val | softint, xc);

56 return setRegWithEffect(miscReg, val | softint, tc);

57
58 case MISCREG_TICK_CMPR:
59 if (isNonPriv())
60 return new PrivilegedOpcode;
61 if (tickCompare == NULL)

62 tickCompare = new TickCompareEvent(this, xc);

62 tickCompare = new TickCompareEvent(this, tc);

63 setReg(miscReg, val);
64 if (tick_cmprFields.int_dis && tickCompare.scheduled())
65 tickCompare.deschedule();
66 time = tick_cmprFields.tick_cmpr - tickFields.counter;
67 if (!tick_cmprFields.int_dis && time > 0)

68 tickCompare.schedule(time * xc->getCpuPtr()->cycles(1));

68 tickCompare.schedule(time * tc->getCpuPtr()->cycles(1));

69 return NoFault;
70
71 case MISCREG_STICK:
72 if (isNonPriv())
73 return new PrivilegedOpcode;
74 if (isPriv())
75 return new PrivilegedAction;

76 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());

76 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());

77 assert(sys != NULL);
78 sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
79 stickFields.npt = val & Bit64 ? 1 : 0;
80 return NoFault;
81
82 case MISCREG_STICK_CMPR:
83 if (isNonPriv())
84 return new PrivilegedOpcode;
85 if (sTickCompare == NULL)

86 sTickCompare = new STickCompareEvent(this, xc);
87 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());

86 sTickCompare = new STickCompareEvent(this, tc);
87 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());

88 assert(sys != NULL);
89 setReg(miscReg, val);
90 if (stick_cmprFields.int_dis && sTickCompare.scheduled())
91 sTickCompare.deschedule();
92 time = stick_cmprFields.tick_cmpr - sys->sysTick;
93 if (!stick_cmprFields.int_dis && time > 0)
94 sTickCompare.schedule(time * Clock::Int::ns);
95 return NoFault;
96
97 /** Fullsystem only Priv registers. */
98 case MISCREG_PIL:
99 if (FULL_SYSTEM) {
100 setReg(miscReg, val);

101 //xc->getCpuPtr()->checkInterrupts;

101 //tc->getCpuPtr()->checkInterrupts;

102 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
103 return NoFault;
104 } else
105 panic("PIL not implemented for syscall emulation\n");
106
107 /** Hyper privileged registers */
108 case MISCREG_HPSTATE:
109 case MISCREG_HINTP:

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122
123 case MISCREG_STRAND_STS_REG:
124 setReg(miscReg, strandStatusReg);
125 return NoFault;
126 case MISCREG_HSTICK_CMPR:
127 if (isNonPriv())
128 return new PrivilegedOpcode;
129 if (hSTickCompare == NULL)

130 hSTickCompare = new HSTickCompareEvent(this, xc);
131 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());

130 hSTickCompare = new HSTickCompareEvent(this, tc);
131 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());

132 assert(sys != NULL);
133 setReg(miscReg, val);
134 if (hstick_cmprFields.int_dis && hSTickCompare.scheduled())
135 hSTickCompare.deschedule();
136 int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick;
137 if (!hstick_cmprFields.int_dis && time > 0)
138 hSTickCompare.schedule(time * Clock::Int::ns);
139 return NoFault;
140 default:
141 return new IllegalInstruction;
142 }
143}
144
145MiscReg

146MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc)

146MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc)

147{
148 switch (miscReg) {
149
150 /** Privileged registers. */
151 case MISCREG_SOFTINT:
152 if (isNonPriv()) {
153 fault = new PrivilegedOpcode;
154 return 0;

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161 }
162 return readReg(miscReg);
163 case MISCREG_STICK:
164 SparcSystem *sys;
165 if (stickFields.npt && !isNonPriv()) {
166 fault = new PrivilegedAction;
167 return 0;
168 }

169 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());

169 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());

170 assert(sys != NULL);
171 return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
172 case MISCREG_STICK_CMPR:
173 if (isNonPriv()) {
174 fault = new PrivilegedOpcode;
175 return 0;
176 }
177 return readReg(miscReg);

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199
200 default:
201 fault = new IllegalInstruction;
202 return 0;
203 }
204}
205
206void

207MiscRegFile::processTickCompare(ExecContext *xc)

207MiscRegFile::processTickCompare(ThreadContext *tc)

208{
209 panic("tick compare not implemented\n");
210}
211
212void

213MiscRegFile::processSTickCompare(ExecContext *xc)

213MiscRegFile::processSTickCompare(ThreadContext *tc)

214{
215 panic("tick compare not implemented\n");
216}
217
218void

219MiscRegFile::processHSTickCompare(ExecContext *xc)

219MiscRegFile::processHSTickCompare(ThreadContext *tc)