ua2005.cc (13582:989577bf6abc) ua2005.cc (13583:f7482392b097)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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83 "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
84 "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
85 "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
86 "nresErrorHead", "nresErrorTail", "TlbData" };
87 return miscRegName[index];
88}
89
90void
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 74 unchanged lines hidden (view full) ---

83 "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
84 "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
85 "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
86 "nresErrorHead", "nresErrorTail", "TlbData" };
87 return miscRegName[index];
88}
89
90void
91ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc)
91ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc)
92{
93 BaseCPU *cpu = tc->getCpuPtr();
94
95 int64_t time;
96 switch (miscReg) {
97 /* Full system only ASRs */
98 case MISCREG_SOFTINT:
99 setMiscRegNoEffect(miscReg, val);;

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237 break;
238
239 default:
240 panic("Invalid write to FS misc register %s\n",
241 getMiscRegName(miscReg));
242 }
243}
244
92{
93 BaseCPU *cpu = tc->getCpuPtr();
94
95 int64_t time;
96 switch (miscReg) {
97 /* Full system only ASRs */
98 case MISCREG_SOFTINT:
99 setMiscRegNoEffect(miscReg, val);;

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237 break;
238
239 default:
240 panic("Invalid write to FS misc register %s\n",
241 getMiscRegName(miscReg));
242 }
243}
244
245MiscReg
245RegVal
246ISA::readFSReg(int miscReg, ThreadContext * tc)
247{
248 uint64_t temp;
249
250 switch (miscReg) {
251 /* Privileged registers. */
252 case MISCREG_QUEUE_CPU_MONDO_HEAD:
253 case MISCREG_QUEUE_CPU_MONDO_TAIL:

--- 123 unchanged lines hidden --- 		246ISA::readFSReg(int miscReg, ThreadContext * tc)
247{
248 uint64_t temp;
249
250 switch (miscReg) {
251 /* Privileged registers. */
252 case MISCREG_QUEUE_CPU_MONDO_HEAD:
253 case MISCREG_QUEUE_CPU_MONDO_TAIL:

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