ua2005.cc (11102:c77f3a9e59bb) ua2005.cc (11150:a8a64cca231b)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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44
45void
46ISA::checkSoftInt(ThreadContext *tc)
47{
48 BaseCPU *cpu = tc->getCpuPtr();
49
50 // If PIL < 14, copy over the tm and sm bits
51 if (pil < 14 && softint & 0x10000)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 35 unchanged lines hidden (view full) ---

44
45void
46ISA::checkSoftInt(ThreadContext *tc)
47{
48 BaseCPU *cpu = tc->getCpuPtr();
49
50 // If PIL < 14, copy over the tm and sm bits
51 if (pil < 14 && softint & 0x10000)
52 cpu->postInterrupt(IT_SOFT_INT, 16);
52 cpu->postInterrupt(0, IT_SOFT_INT, 16);
53 else
53 else
54 cpu->clearInterrupt(IT_SOFT_INT, 16);
54 cpu->clearInterrupt(0, IT_SOFT_INT, 16);
55 if (pil < 14 && softint & 0x1)
55 if (pil < 14 && softint & 0x1)
56 cpu->postInterrupt(IT_SOFT_INT, 0);
56 cpu->postInterrupt(0, IT_SOFT_INT, 0);
57 else
57 else
58 cpu->clearInterrupt(IT_SOFT_INT, 0);
58 cpu->clearInterrupt(0, IT_SOFT_INT, 0);
59
60 // Copy over any of the other bits that are set
61 for (int bit = 15; bit > 0; --bit) {
62 if (1 << bit & softint && bit > pil)
59
60 // Copy over any of the other bits that are set
61 for (int bit = 15; bit > 0; --bit) {
62 if (1 << bit & softint && bit > pil)
63 cpu->postInterrupt(IT_SOFT_INT, bit);
63 cpu->postInterrupt(0, IT_SOFT_INT, bit);
64 else
64 else
65 cpu->clearInterrupt(IT_SOFT_INT, bit);
65 cpu->clearInterrupt(0, IT_SOFT_INT, bit);
66 }
67}
68
69// These functions map register indices to names
70static inline string
71getMiscRegName(RegIndex index)
72{
73 static string miscRegName[NumMiscRegs] =

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144 break;
145
146 case MISCREG_HVER:
147 panic("Shouldn't be writing HVER\n");
148
149 case MISCREG_HINTP:
150 setMiscRegNoEffect(miscReg, val);
151 if (hintp)
66 }
67}
68
69// These functions map register indices to names
70static inline string
71getMiscRegName(RegIndex index)
72{
73 static string miscRegName[NumMiscRegs] =

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144 break;
145
146 case MISCREG_HVER:
147 panic("Shouldn't be writing HVER\n");
148
149 case MISCREG_HINTP:
150 setMiscRegNoEffect(miscReg, val);
151 if (hintp)
152 cpu->postInterrupt(IT_HINTP, 0);
152 cpu->postInterrupt(0, IT_HINTP, 0);
153 else
153 else
154 cpu->clearInterrupt(IT_HINTP, 0);
154 cpu->clearInterrupt(0, IT_HINTP, 0);
155 break;
156
157 case MISCREG_HTBA:
158 // clear lower 7 bits on writes.
159 setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF));
160 break;
161
162 case MISCREG_QUEUE_CPU_MONDO_HEAD:
163 case MISCREG_QUEUE_CPU_MONDO_TAIL:
164 setMiscRegNoEffect(miscReg, val);
165 if (cpu_mondo_head != cpu_mondo_tail)
155 break;
156
157 case MISCREG_HTBA:
158 // clear lower 7 bits on writes.
159 setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF));
160 break;
161
162 case MISCREG_QUEUE_CPU_MONDO_HEAD:
163 case MISCREG_QUEUE_CPU_MONDO_TAIL:
164 setMiscRegNoEffect(miscReg, val);
165 if (cpu_mondo_head != cpu_mondo_tail)
166 cpu->postInterrupt(IT_CPU_MONDO, 0);
166 cpu->postInterrupt(0, IT_CPU_MONDO, 0);
167 else
167 else
168 cpu->clearInterrupt(IT_CPU_MONDO, 0);
168 cpu->clearInterrupt(0, IT_CPU_MONDO, 0);
169 break;
170 case MISCREG_QUEUE_DEV_MONDO_HEAD:
171 case MISCREG_QUEUE_DEV_MONDO_TAIL:
172 setMiscRegNoEffect(miscReg, val);
173 if (dev_mondo_head != dev_mondo_tail)
169 break;
170 case MISCREG_QUEUE_DEV_MONDO_HEAD:
171 case MISCREG_QUEUE_DEV_MONDO_TAIL:
172 setMiscRegNoEffect(miscReg, val);
173 if (dev_mondo_head != dev_mondo_tail)
174 cpu->postInterrupt(IT_DEV_MONDO, 0);
174 cpu->postInterrupt(0, IT_DEV_MONDO, 0);
175 else
175 else
176 cpu->clearInterrupt(IT_DEV_MONDO, 0);
176 cpu->clearInterrupt(0, IT_DEV_MONDO, 0);
177 break;
178 case MISCREG_QUEUE_RES_ERROR_HEAD:
179 case MISCREG_QUEUE_RES_ERROR_TAIL:
180 setMiscRegNoEffect(miscReg, val);
181 if (res_error_head != res_error_tail)
177 break;
178 case MISCREG_QUEUE_RES_ERROR_HEAD:
179 case MISCREG_QUEUE_RES_ERROR_TAIL:
180 setMiscRegNoEffect(miscReg, val);
181 if (res_error_head != res_error_tail)
182 cpu->postInterrupt(IT_RES_ERROR, 0);
182 cpu->postInterrupt(0, IT_RES_ERROR, 0);
183 else
183 else
184 cpu->clearInterrupt(IT_RES_ERROR, 0);
184 cpu->clearInterrupt(0, IT_RES_ERROR, 0);
185 break;
186 case MISCREG_QUEUE_NRES_ERROR_HEAD:
187 case MISCREG_QUEUE_NRES_ERROR_TAIL:
188 setMiscRegNoEffect(miscReg, val);
189 // This one doesn't have an interrupt to report to the guest OS
190 break;
191
192 case MISCREG_HSTICK_CMPR:

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208 case MISCREG_HPSTATE:
209 {
210 HPSTATE newVal = val;
211 newVal.id = 1;
212 // T1000 spec says impl. dependent val must always be 1
213 setMiscRegNoEffect(miscReg, newVal);
214 newVal = hpstate;
215 if (newVal.tlz && tl == 0 && !newVal.hpriv)
185 break;
186 case MISCREG_QUEUE_NRES_ERROR_HEAD:
187 case MISCREG_QUEUE_NRES_ERROR_TAIL:
188 setMiscRegNoEffect(miscReg, val);
189 // This one doesn't have an interrupt to report to the guest OS
190 break;
191
192 case MISCREG_HSTICK_CMPR:

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208 case MISCREG_HPSTATE:
209 {
210 HPSTATE newVal = val;
211 newVal.id = 1;
212 // T1000 spec says impl. dependent val must always be 1
213 setMiscRegNoEffect(miscReg, newVal);
214 newVal = hpstate;
215 if (newVal.tlz && tl == 0 && !newVal.hpriv)
216 cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
216 cpu->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
217 else
217 else
218 cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
218 cpu->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
219 break;
220 }
221 case MISCREG_HTSTATE:
222 setMiscRegNoEffect(miscReg, val);
223 break;
224
225 case MISCREG_STRAND_STS_REG:
226 if (bits(val,2,2))

--- 149 unchanged lines hidden --- 		219 break;
220 }
221 case MISCREG_HTSTATE:
222 setMiscRegNoEffect(miscReg, val);
223 break;
224
225 case MISCREG_STRAND_STS_REG:
226 if (bits(val,2,2))

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