1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 22 unchanged lines hidden (view full) --- 31#include "arch/sparc/registers.hh" 32#include "base/bitfield.hh" 33#include "base/trace.hh" 34#include "cpu/base.hh" 35#include "cpu/thread_context.hh" 36#include "debug/Quiesce.hh" 37#include "debug/Timer.hh" 38#include "sim/system.hh" |
39#include "sim/full_system.hh" |
40 41using namespace SparcISA; 42using namespace std; 43 44 45void 46ISA::checkSoftInt(ThreadContext *tc) 47{ --- 172 unchanged lines hidden (view full) --- 220 case MISCREG_STRAND_STS_REG: 221 if (bits(val,2,2)) 222 panic("No support for setting spec_en bit\n"); 223 setMiscRegNoEffect(miscReg, bits(val,0,0)); 224 if (!bits(val,0,0)) { 225 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); 226 // Time to go to sleep 227 tc->suspend(); |
228 if (FullSystem && tc->getKernelStats()) |
229 tc->getKernelStats()->quiesce(); |
230 } 231 break; 232 233 default: 234 panic("Invalid write to FS misc register %s\n", 235 getMiscRegName(miscReg)); 236 } 237} --- 133 unchanged lines hidden --- |