1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 28 unchanged lines hidden (view full) --- 37void 38MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 39 ThreadContext *tc) 40{ 41 int64_t time; 42 switch (miscReg) { 43 /* Full system only ASRs */ 44 case MISCREG_SOFTINT: |
45 setReg(miscReg, val);; |
46 if (val != 0x10000 && val != 0) 47 warn("Writing to softint not really supported, writing: %#x\n", val); 48 break; 49 50 case MISCREG_SOFTINT_CLR: 51 return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc); 52 case MISCREG_SOFTINT_SET: |
53 tc->getCpuPtr()->checkInterrupts = true; 54 tc->getCpuPtr()->post_interrupt(soft_interrupt); |
55 return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc); 56 57 case MISCREG_TICK_CMPR: 58 if (tickCompare == NULL) 59 tickCompare = new TickCompareEvent(this, tc); 60 setReg(miscReg, val); 61 if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) 62 tickCompare->deschedule(); --- 27 unchanged lines hidden (view full) --- 90 tc->getCpuPtr()->checkInterrupts = true; 91 } 92 setReg(miscReg, val); 93 break; 94 95 case MISCREG_HVER: 96 panic("Shouldn't be writing HVER\n"); 97 |
98 case MISCREG_HINTP: 99 setReg(miscReg, val); 100 |
101 case MISCREG_HTBA: 102 // clear lower 7 bits on writes. 103 setReg(miscReg, val & ULL(~0x7FFF)); 104 break; 105 106 case MISCREG_QUEUE_CPU_MONDO_HEAD: 107 case MISCREG_QUEUE_CPU_MONDO_TAIL: 108 case MISCREG_QUEUE_DEV_MONDO_HEAD: --- 92 unchanged lines hidden (view full) --- 201 int ticks; 202 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 203 tc->getCpuPtr()->instCount(); 204 assert(ticks >= 0 && "stick compare missed interrupt cycle"); 205 206 if (ticks == 0) { 207 DPRINTF(Timer, "STick compare cycle reached at %#x\n", 208 (stick_cmpr & mask(63))); |
209 if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 210 tc->getCpuPtr()->post_interrupt(soft_interrupt); 211 tc->getCpuPtr()->checkInterrupts = true; 212 setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 213 } |
214 } else 215 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 216} 217 218void 219MiscRegFile::processHSTickCompare(ThreadContext *tc) 220{ 221 // since our microcode instructions take two cycles we need to check if 222 // we're actually at the correct cycle or we need to wait a little while 223 // more 224 int ticks; 225 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 226 tc->getCpuPtr()->instCount(); 227 assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 228 229 if (ticks == 0) { 230 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 231 (stick_cmpr & mask(63))); |
232 if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 233 setRegWithEffect(MISCREG_HINTP, 1, tc); 234 tc->getCpuPtr()->post_interrupt(hstick_match); 235 tc->getCpuPtr()->checkInterrupts = true; 236 } |
237 // Need to do something to cause interrupt to happen here !!! @todo 238 } else 239 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 240} 241 |