31c31,35
< #include "arch/sparc/regfile.hh"
---
> #include "arch/sparc/miscregfile.hh"
> #include "base/bitfield.hh"
> #include "base/trace.hh"
> #include "cpu/base.hh"
> #include "cpu/thread_context.hh"
33,34c37,40
< Fault
< SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
---
> using namespace SparcISA;
>
> void
> MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
38c44
< SparcSystem *sys;
---
> int oldLevel, newLevel;
42,43d47
< if (isNonPriv())
< return new PrivilegedOpcode;
45,46c49,50
< int oldLevel = InterruptLevel(softint);
< int newLevel = InterruptLevel(val);
---
> oldLevel = InterruptLevel(softint);
> newLevel = InterruptLevel(val);
51c55,56
< return NoFault;
---
> panic("SOFTINT not implemented\n");
> break;
59,60d63
< if (isNonPriv())
< return new PrivilegedOpcode;
64,69c67,72
< if (tick_cmprFields.int_dis && tickCompare.scheduled())
< tickCompare.deschedule();
< time = tick_cmprFields.tick_cmpr - tickFields.counter;
< if (!tick_cmprFields.int_dis && time > 0)
< tickCompare.schedule(time * tc->getCpuPtr()->cycles(1));
< return NoFault;
---
> if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
> tickCompare->deschedule();
> time = (tick_cmpr & mask(63)) - (tick & mask(63));
> if (!(tick_cmpr & ~mask(63)) && time > 0)
> tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
> break;
71,81d73
< case MISCREG_STICK:
< if (isNonPriv())
< return new PrivilegedOpcode;
< if (isPriv())
< return new PrivilegedAction;
< sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
< assert(sys != NULL);
< sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
< stickFields.npt = val & Bit64 ? 1 : 0;
< return NoFault;
<
83,84d74
< if (isNonPriv())
< return new PrivilegedOpcode;
87,88d76
< sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
< assert(sys != NULL);
90,95c78,83
< if (stick_cmprFields.int_dis && sTickCompare.scheduled())
< sTickCompare.deschedule();
< time = stick_cmprFields.tick_cmpr - sys->sysTick;
< if (!stick_cmprFields.int_dis && time > 0)
< sTickCompare.schedule(time * Clock::Int::ns);
< return NoFault;
---
> if ((stick_cmpr & mask(63)) && sTickCompare->scheduled())
> sTickCompare->deschedule();
> time = (stick_cmpr & mask(63)) - (stick & mask(63));
> if (!(stick_cmpr & ~mask(63)) && time > 0)
> sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
> break;
97d84
< /* Fullsystem only Priv registers. */
99,109d85
< if (FULL_SYSTEM) {
< setReg(miscReg, val);
< //tc->getCpuPtr()->checkInterrupts;
< // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
< return NoFault;
< } else
< panic("PIL not implemented for syscall emulation\n");
<
< /* Hyper privileged registers */
< case MISCREG_HPSTATE:
< case MISCREG_HINTP:
111,116c87,90
< return NoFault;
< case MISCREG_HTSTATE:
< if (tl == 0)
< return new IllegalInstruction;
< setReg(miscReg, val);
< return NoFault;
---
> //tc->getCpuPtr()->checkInterrupts;
> // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
> panic("PIL not implemented\n");
> break;
117a92,94
> case MISCREG_HVER:
> panic("Shouldn't be writing HVER\n");
>
121c98
< return NoFault;
---
> break;
123,125d99
< case MISCREG_STRAND_STS_REG:
< setReg(miscReg, strandStatusReg);
< return NoFault;
127,128d100
< if (isNonPriv())
< return new PrivilegedOpcode;
131,132d102
< sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
< assert(sys != NULL);
134,139c104,116
< if (hstick_cmprFields.int_dis && hSTickCompare.scheduled())
< hSTickCompare.deschedule();
< int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick;
< if (!hstick_cmprFields.int_dis && time > 0)
< hSTickCompare.schedule(time * Clock::Int::ns);
< return NoFault;
---
> if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled())
> hSTickCompare->deschedule();
> time = (hstick_cmpr & mask(63)) - (stick & mask(63));
> if (!(hstick_cmpr & ~mask(63)) && time > 0)
> hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
> break;
>
> case MISCREG_HPSTATE:
> case MISCREG_HTSTATE:
> case MISCREG_STRAND_STS_REG:
> setReg(miscReg, val);
> break;
>
141c118
< return new IllegalInstruction;
---
> panic("Invalid write to FS misc register\n");
146c123
< MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc)
---
> MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
152,156d128
< if (isNonPriv()) {
< fault = new PrivilegedOpcode;
< return 0;
< }
< return readReg(miscReg);
158,171d129
< if (isNonPriv()) {
< fault = new PrivilegedOpcode;
< return 0;
< }
< return readReg(miscReg);
< case MISCREG_STICK:
< SparcSystem *sys;
< if (stickFields.npt && !isNonPriv()) {
< fault = new PrivilegedAction;
< return 0;
< }
< sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
< assert(sys != NULL);
< return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
173,180c131
< if (isNonPriv()) {
< fault = new PrivilegedOpcode;
< return 0;
< }
< return readReg(miscReg);
<
<
< /* Hyper privileged registers */
---
> case MISCREG_PIL:
183d133
< return readReg(miscReg);
185,189c135,137
< if (tl == 0) {
< fault = new IllegalInstruction;
< return 0;
< }
< return readReg(miscReg);
---
> case MISCREG_STRAND_STS_REG:
> case MISCREG_HSTICK_CMPR:
> return readReg(miscReg) ;
195,198d142
< case MISCREG_STRAND_STS_REG:
< return strandStatusReg;
< case MISCREG_HSTICK_CMPR:
< return hstick_cmpr;
201,202c145
< fault = new IllegalInstruction;
< return 0;
---
> panic("Invalid read to FS misc register\n");
204a148,155
> /*
> In Niagra STICK==TICK so this isn't needed
> case MISCREG_STICK:
> SparcSystem *sys;
> sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
> assert(sys != NULL);
> return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
> */
205a157,158
>
>
224d176
< }; // namespace SparcISA