1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "arch/sparc/isa.hh" 30#include "arch/sparc/kernel_stats.hh" 31#include "arch/sparc/registers.hh" 32#include "base/bitfield.hh" 33#include "base/trace.hh" 34#include "cpu/base.hh" 35#include "cpu/thread_context.hh" 36#include "debug/Quiesce.hh" 37#include "debug/Timer.hh" 38#include "sim/system.hh"
| 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "arch/sparc/isa.hh" 30#include "arch/sparc/kernel_stats.hh" 31#include "arch/sparc/registers.hh" 32#include "base/bitfield.hh" 33#include "base/trace.hh" 34#include "cpu/base.hh" 35#include "cpu/thread_context.hh" 36#include "debug/Quiesce.hh" 37#include "debug/Timer.hh" 38#include "sim/system.hh"
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39 40using namespace SparcISA; 41using namespace std; 42 43 44void 45ISA::checkSoftInt(ThreadContext *tc) 46{ 47 BaseCPU *cpu = tc->getCpuPtr(); 48 49 // If PIL < 14, copy over the tm and sm bits 50 if (pil < 14 && softint & 0x10000) 51 cpu->postInterrupt(IT_SOFT_INT, 16); 52 else 53 cpu->clearInterrupt(IT_SOFT_INT, 16); 54 if (pil < 14 && softint & 0x1) 55 cpu->postInterrupt(IT_SOFT_INT, 0); 56 else 57 cpu->clearInterrupt(IT_SOFT_INT, 0); 58 59 // Copy over any of the other bits that are set 60 for (int bit = 15; bit > 0; --bit) { 61 if (1 << bit & softint && bit > pil) 62 cpu->postInterrupt(IT_SOFT_INT, bit); 63 else 64 cpu->clearInterrupt(IT_SOFT_INT, bit); 65 } 66} 67 68// These functions map register indices to names 69static inline string 70getMiscRegName(RegIndex index) 71{ 72 static string miscRegName[NumMiscRegs] = 73 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", 74 "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", 75 "stick", "stick_cmpr", 76 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", 77 "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", 78 "wstate",*/ "gl", 79 "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", 80 "hstick_cmpr", 81 "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", 82 "scratch0", "scratch1", "scratch2", "scratch3", "scratch4", 83 "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail", 84 "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail", 85 "nresErrorHead", "nresErrorTail", "TlbData" }; 86 return miscRegName[index]; 87} 88 89void 90ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) 91{ 92 BaseCPU *cpu = tc->getCpuPtr(); 93 94 int64_t time; 95 switch (miscReg) { 96 /* Full system only ASRs */ 97 case MISCREG_SOFTINT: 98 setMiscRegNoEffect(miscReg, val);; 99 checkSoftInt(tc); 100 break; 101 case MISCREG_SOFTINT_CLR: 102 return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); 103 case MISCREG_SOFTINT_SET: 104 return setMiscReg(MISCREG_SOFTINT, val | softint, tc); 105 106 case MISCREG_TICK_CMPR: 107 if (tickCompare == NULL) 108 tickCompare = new TickCompareEvent(this, tc); 109 setMiscRegNoEffect(miscReg, val); 110 if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 111 cpu->deschedule(tickCompare); 112 time = (tick_cmpr & mask(63)) - (tick & mask(63)); 113 if (!(tick_cmpr & ~mask(63)) && time > 0) { 114 if (tickCompare->scheduled()) 115 cpu->deschedule(tickCompare); 116 cpu->schedule(tickCompare, curTick() + time * cpu->ticks(1)); 117 } 118 panic("writing to TICK compare register %#X\n", val); 119 break; 120 121 case MISCREG_STICK_CMPR: 122 if (sTickCompare == NULL) 123 sTickCompare = new STickCompareEvent(this, tc); 124 setMiscRegNoEffect(miscReg, val); 125 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 126 cpu->deschedule(sTickCompare); 127 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 128 cpu->instCount(); 129 if (!(stick_cmpr & ~mask(63)) && time > 0) { 130 if (sTickCompare->scheduled()) 131 cpu->deschedule(sTickCompare); 132 cpu->schedule(sTickCompare, curTick() + time * cpu->ticks(1)); 133 } 134 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 135 break; 136 137 case MISCREG_PSTATE: 138 setMiscRegNoEffect(miscReg, val); 139 140 case MISCREG_PIL: 141 setMiscRegNoEffect(miscReg, val); 142 checkSoftInt(tc); 143 break; 144 145 case MISCREG_HVER: 146 panic("Shouldn't be writing HVER\n"); 147 148 case MISCREG_HINTP: 149 setMiscRegNoEffect(miscReg, val); 150 if (hintp) 151 cpu->postInterrupt(IT_HINTP, 0); 152 else 153 cpu->clearInterrupt(IT_HINTP, 0); 154 break; 155 156 case MISCREG_HTBA: 157 // clear lower 7 bits on writes. 158 setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF)); 159 break; 160 161 case MISCREG_QUEUE_CPU_MONDO_HEAD: 162 case MISCREG_QUEUE_CPU_MONDO_TAIL: 163 setMiscRegNoEffect(miscReg, val); 164 if (cpu_mondo_head != cpu_mondo_tail) 165 cpu->postInterrupt(IT_CPU_MONDO, 0); 166 else 167 cpu->clearInterrupt(IT_CPU_MONDO, 0); 168 break; 169 case MISCREG_QUEUE_DEV_MONDO_HEAD: 170 case MISCREG_QUEUE_DEV_MONDO_TAIL: 171 setMiscRegNoEffect(miscReg, val); 172 if (dev_mondo_head != dev_mondo_tail) 173 cpu->postInterrupt(IT_DEV_MONDO, 0); 174 else 175 cpu->clearInterrupt(IT_DEV_MONDO, 0); 176 break; 177 case MISCREG_QUEUE_RES_ERROR_HEAD: 178 case MISCREG_QUEUE_RES_ERROR_TAIL: 179 setMiscRegNoEffect(miscReg, val); 180 if (res_error_head != res_error_tail) 181 cpu->postInterrupt(IT_RES_ERROR, 0); 182 else 183 cpu->clearInterrupt(IT_RES_ERROR, 0); 184 break; 185 case MISCREG_QUEUE_NRES_ERROR_HEAD: 186 case MISCREG_QUEUE_NRES_ERROR_TAIL: 187 setMiscRegNoEffect(miscReg, val); 188 // This one doesn't have an interrupt to report to the guest OS 189 break; 190 191 case MISCREG_HSTICK_CMPR: 192 if (hSTickCompare == NULL) 193 hSTickCompare = new HSTickCompareEvent(this, tc); 194 setMiscRegNoEffect(miscReg, val); 195 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 196 cpu->deschedule(hSTickCompare); 197 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 198 cpu->instCount(); 199 if (!(hstick_cmpr & ~mask(63)) && time > 0) { 200 if (hSTickCompare->scheduled()) 201 cpu->deschedule(hSTickCompare); 202 cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1)); 203 } 204 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 205 break; 206 207 case MISCREG_HPSTATE: 208 // T1000 spec says impl. dependent val must always be 1 209 setMiscRegNoEffect(miscReg, val | HPSTATE::id); 210 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) 211 cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); 212 else 213 cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); 214 break; 215 case MISCREG_HTSTATE: 216 setMiscRegNoEffect(miscReg, val); 217 break; 218 219 case MISCREG_STRAND_STS_REG: 220 if (bits(val,2,2)) 221 panic("No support for setting spec_en bit\n"); 222 setMiscRegNoEffect(miscReg, bits(val,0,0)); 223 if (!bits(val,0,0)) { 224 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); 225 // Time to go to sleep 226 tc->suspend();
| 40 41using namespace SparcISA; 42using namespace std; 43 44 45void 46ISA::checkSoftInt(ThreadContext *tc) 47{ 48 BaseCPU *cpu = tc->getCpuPtr(); 49 50 // If PIL < 14, copy over the tm and sm bits 51 if (pil < 14 && softint & 0x10000) 52 cpu->postInterrupt(IT_SOFT_INT, 16); 53 else 54 cpu->clearInterrupt(IT_SOFT_INT, 16); 55 if (pil < 14 && softint & 0x1) 56 cpu->postInterrupt(IT_SOFT_INT, 0); 57 else 58 cpu->clearInterrupt(IT_SOFT_INT, 0); 59 60 // Copy over any of the other bits that are set 61 for (int bit = 15; bit > 0; --bit) { 62 if (1 << bit & softint && bit > pil) 63 cpu->postInterrupt(IT_SOFT_INT, bit); 64 else 65 cpu->clearInterrupt(IT_SOFT_INT, bit); 66 } 67} 68 69// These functions map register indices to names 70static inline string 71getMiscRegName(RegIndex index) 72{ 73 static string miscRegName[NumMiscRegs] = 74 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", 75 "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", 76 "stick", "stick_cmpr", 77 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", 78 "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", 79 "wstate",*/ "gl", 80 "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", 81 "hstick_cmpr", 82 "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", 83 "scratch0", "scratch1", "scratch2", "scratch3", "scratch4", 84 "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail", 85 "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail", 86 "nresErrorHead", "nresErrorTail", "TlbData" }; 87 return miscRegName[index]; 88} 89 90void 91ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc) 92{ 93 BaseCPU *cpu = tc->getCpuPtr(); 94 95 int64_t time; 96 switch (miscReg) { 97 /* Full system only ASRs */ 98 case MISCREG_SOFTINT: 99 setMiscRegNoEffect(miscReg, val);; 100 checkSoftInt(tc); 101 break; 102 case MISCREG_SOFTINT_CLR: 103 return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); 104 case MISCREG_SOFTINT_SET: 105 return setMiscReg(MISCREG_SOFTINT, val | softint, tc); 106 107 case MISCREG_TICK_CMPR: 108 if (tickCompare == NULL) 109 tickCompare = new TickCompareEvent(this, tc); 110 setMiscRegNoEffect(miscReg, val); 111 if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 112 cpu->deschedule(tickCompare); 113 time = (tick_cmpr & mask(63)) - (tick & mask(63)); 114 if (!(tick_cmpr & ~mask(63)) && time > 0) { 115 if (tickCompare->scheduled()) 116 cpu->deschedule(tickCompare); 117 cpu->schedule(tickCompare, curTick() + time * cpu->ticks(1)); 118 } 119 panic("writing to TICK compare register %#X\n", val); 120 break; 121 122 case MISCREG_STICK_CMPR: 123 if (sTickCompare == NULL) 124 sTickCompare = new STickCompareEvent(this, tc); 125 setMiscRegNoEffect(miscReg, val); 126 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 127 cpu->deschedule(sTickCompare); 128 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 129 cpu->instCount(); 130 if (!(stick_cmpr & ~mask(63)) && time > 0) { 131 if (sTickCompare->scheduled()) 132 cpu->deschedule(sTickCompare); 133 cpu->schedule(sTickCompare, curTick() + time * cpu->ticks(1)); 134 } 135 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 136 break; 137 138 case MISCREG_PSTATE: 139 setMiscRegNoEffect(miscReg, val); 140 141 case MISCREG_PIL: 142 setMiscRegNoEffect(miscReg, val); 143 checkSoftInt(tc); 144 break; 145 146 case MISCREG_HVER: 147 panic("Shouldn't be writing HVER\n"); 148 149 case MISCREG_HINTP: 150 setMiscRegNoEffect(miscReg, val); 151 if (hintp) 152 cpu->postInterrupt(IT_HINTP, 0); 153 else 154 cpu->clearInterrupt(IT_HINTP, 0); 155 break; 156 157 case MISCREG_HTBA: 158 // clear lower 7 bits on writes. 159 setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF)); 160 break; 161 162 case MISCREG_QUEUE_CPU_MONDO_HEAD: 163 case MISCREG_QUEUE_CPU_MONDO_TAIL: 164 setMiscRegNoEffect(miscReg, val); 165 if (cpu_mondo_head != cpu_mondo_tail) 166 cpu->postInterrupt(IT_CPU_MONDO, 0); 167 else 168 cpu->clearInterrupt(IT_CPU_MONDO, 0); 169 break; 170 case MISCREG_QUEUE_DEV_MONDO_HEAD: 171 case MISCREG_QUEUE_DEV_MONDO_TAIL: 172 setMiscRegNoEffect(miscReg, val); 173 if (dev_mondo_head != dev_mondo_tail) 174 cpu->postInterrupt(IT_DEV_MONDO, 0); 175 else 176 cpu->clearInterrupt(IT_DEV_MONDO, 0); 177 break; 178 case MISCREG_QUEUE_RES_ERROR_HEAD: 179 case MISCREG_QUEUE_RES_ERROR_TAIL: 180 setMiscRegNoEffect(miscReg, val); 181 if (res_error_head != res_error_tail) 182 cpu->postInterrupt(IT_RES_ERROR, 0); 183 else 184 cpu->clearInterrupt(IT_RES_ERROR, 0); 185 break; 186 case MISCREG_QUEUE_NRES_ERROR_HEAD: 187 case MISCREG_QUEUE_NRES_ERROR_TAIL: 188 setMiscRegNoEffect(miscReg, val); 189 // This one doesn't have an interrupt to report to the guest OS 190 break; 191 192 case MISCREG_HSTICK_CMPR: 193 if (hSTickCompare == NULL) 194 hSTickCompare = new HSTickCompareEvent(this, tc); 195 setMiscRegNoEffect(miscReg, val); 196 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 197 cpu->deschedule(hSTickCompare); 198 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 199 cpu->instCount(); 200 if (!(hstick_cmpr & ~mask(63)) && time > 0) { 201 if (hSTickCompare->scheduled()) 202 cpu->deschedule(hSTickCompare); 203 cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1)); 204 } 205 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 206 break; 207 208 case MISCREG_HPSTATE: 209 // T1000 spec says impl. dependent val must always be 1 210 setMiscRegNoEffect(miscReg, val | HPSTATE::id); 211 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv)) 212 cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0); 213 else 214 cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0); 215 break; 216 case MISCREG_HTSTATE: 217 setMiscRegNoEffect(miscReg, val); 218 break; 219 220 case MISCREG_STRAND_STS_REG: 221 if (bits(val,2,2)) 222 panic("No support for setting spec_en bit\n"); 223 setMiscRegNoEffect(miscReg, bits(val,0,0)); 224 if (!bits(val,0,0)) { 225 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); 226 // Time to go to sleep 227 tc->suspend();
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