ua2005.cc (7741:340b6f01d69b) ua2005.cc (7823:dac01f14f20f)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/sparc/isa.hh"
30#include "arch/sparc/kernel_stats.hh"
31#include "arch/sparc/registers.hh"
32#include "base/bitfield.hh"
33#include "base/trace.hh"
34#include "cpu/base.hh"
35#include "cpu/thread_context.hh"
36#include "sim/system.hh"
37
38using namespace SparcISA;
39using namespace std;
40
41
42void
43ISA::checkSoftInt(ThreadContext *tc)
44{
45 BaseCPU *cpu = tc->getCpuPtr();
46
47 // If PIL < 14, copy over the tm and sm bits
48 if (pil < 14 && softint & 0x10000)
49 cpu->postInterrupt(IT_SOFT_INT, 16);
50 else
51 cpu->clearInterrupt(IT_SOFT_INT, 16);
52 if (pil < 14 && softint & 0x1)
53 cpu->postInterrupt(IT_SOFT_INT, 0);
54 else
55 cpu->clearInterrupt(IT_SOFT_INT, 0);
56
57 // Copy over any of the other bits that are set
58 for (int bit = 15; bit > 0; --bit) {
59 if (1 << bit & softint && bit > pil)
60 cpu->postInterrupt(IT_SOFT_INT, bit);
61 else
62 cpu->clearInterrupt(IT_SOFT_INT, bit);
63 }
64}
65
66// These functions map register indices to names
67static inline string
68getMiscRegName(RegIndex index)
69{
70 static string miscRegName[NumMiscRegs] =
71 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
72 "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
73 "stick", "stick_cmpr",
74 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
75 "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
76 "wstate",*/ "gl",
77 "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
78 "hstick_cmpr",
79 "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
80 "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
81 "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
82 "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
83 "nresErrorHead", "nresErrorTail", "TlbData" };
84 return miscRegName[index];
85}
86
87void
88ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
89{
90 BaseCPU *cpu = tc->getCpuPtr();
91
92 int64_t time;
93 switch (miscReg) {
94 /* Full system only ASRs */
95 case MISCREG_SOFTINT:
96 setMiscRegNoEffect(miscReg, val);;
97 checkSoftInt(tc);
98 break;
99 case MISCREG_SOFTINT_CLR:
100 return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc);
101 case MISCREG_SOFTINT_SET:
102 return setMiscReg(MISCREG_SOFTINT, val | softint, tc);
103
104 case MISCREG_TICK_CMPR:
105 if (tickCompare == NULL)
106 tickCompare = new TickCompareEvent(this, tc);
107 setMiscRegNoEffect(miscReg, val);
108 if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
109 cpu->deschedule(tickCompare);
110 time = (tick_cmpr & mask(63)) - (tick & mask(63));
111 if (!(tick_cmpr & ~mask(63)) && time > 0) {
112 if (tickCompare->scheduled())
113 cpu->deschedule(tickCompare);
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/sparc/isa.hh"
30#include "arch/sparc/kernel_stats.hh"
31#include "arch/sparc/registers.hh"
32#include "base/bitfield.hh"
33#include "base/trace.hh"
34#include "cpu/base.hh"
35#include "cpu/thread_context.hh"
36#include "sim/system.hh"
37
38using namespace SparcISA;
39using namespace std;
40
41
42void
43ISA::checkSoftInt(ThreadContext *tc)
44{
45 BaseCPU *cpu = tc->getCpuPtr();
46
47 // If PIL < 14, copy over the tm and sm bits
48 if (pil < 14 && softint & 0x10000)
49 cpu->postInterrupt(IT_SOFT_INT, 16);
50 else
51 cpu->clearInterrupt(IT_SOFT_INT, 16);
52 if (pil < 14 && softint & 0x1)
53 cpu->postInterrupt(IT_SOFT_INT, 0);
54 else
55 cpu->clearInterrupt(IT_SOFT_INT, 0);
56
57 // Copy over any of the other bits that are set
58 for (int bit = 15; bit > 0; --bit) {
59 if (1 << bit & softint && bit > pil)
60 cpu->postInterrupt(IT_SOFT_INT, bit);
61 else
62 cpu->clearInterrupt(IT_SOFT_INT, bit);
63 }
64}
65
66// These functions map register indices to names
67static inline string
68getMiscRegName(RegIndex index)
69{
70 static string miscRegName[NumMiscRegs] =
71 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
72 "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
73 "stick", "stick_cmpr",
74 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
75 "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
76 "wstate",*/ "gl",
77 "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
78 "hstick_cmpr",
79 "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
80 "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
81 "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
82 "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
83 "nresErrorHead", "nresErrorTail", "TlbData" };
84 return miscRegName[index];
85}
86
87void
88ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
89{
90 BaseCPU *cpu = tc->getCpuPtr();
91
92 int64_t time;
93 switch (miscReg) {
94 /* Full system only ASRs */
95 case MISCREG_SOFTINT:
96 setMiscRegNoEffect(miscReg, val);;
97 checkSoftInt(tc);
98 break;
99 case MISCREG_SOFTINT_CLR:
100 return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc);
101 case MISCREG_SOFTINT_SET:
102 return setMiscReg(MISCREG_SOFTINT, val | softint, tc);
103
104 case MISCREG_TICK_CMPR:
105 if (tickCompare == NULL)
106 tickCompare = new TickCompareEvent(this, tc);
107 setMiscRegNoEffect(miscReg, val);
108 if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
109 cpu->deschedule(tickCompare);
110 time = (tick_cmpr & mask(63)) - (tick & mask(63));
111 if (!(tick_cmpr & ~mask(63)) && time > 0) {
112 if (tickCompare->scheduled())
113 cpu->deschedule(tickCompare);
114 cpu->schedule(tickCompare, curTick + time * cpu->ticks(1));
114 cpu->schedule(tickCompare, curTick() + time * cpu->ticks(1));
115 }
116 panic("writing to TICK compare register %#X\n", val);
117 break;
118
119 case MISCREG_STICK_CMPR:
120 if (sTickCompare == NULL)
121 sTickCompare = new STickCompareEvent(this, tc);
122 setMiscRegNoEffect(miscReg, val);
123 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
124 cpu->deschedule(sTickCompare);
125 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
126 cpu->instCount();
127 if (!(stick_cmpr & ~mask(63)) && time > 0) {
128 if (sTickCompare->scheduled())
129 cpu->deschedule(sTickCompare);
115 }
116 panic("writing to TICK compare register %#X\n", val);
117 break;
118
119 case MISCREG_STICK_CMPR:
120 if (sTickCompare == NULL)
121 sTickCompare = new STickCompareEvent(this, tc);
122 setMiscRegNoEffect(miscReg, val);
123 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
124 cpu->deschedule(sTickCompare);
125 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
126 cpu->instCount();
127 if (!(stick_cmpr & ~mask(63)) && time > 0) {
128 if (sTickCompare->scheduled())
129 cpu->deschedule(sTickCompare);
130 cpu->schedule(sTickCompare, curTick + time * cpu->ticks(1));
130 cpu->schedule(sTickCompare, curTick() + time * cpu->ticks(1));
131 }
132 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
133 break;
134
135 case MISCREG_PSTATE:
136 setMiscRegNoEffect(miscReg, val);
137
138 case MISCREG_PIL:
139 setMiscRegNoEffect(miscReg, val);
140 checkSoftInt(tc);
141 break;
142
143 case MISCREG_HVER:
144 panic("Shouldn't be writing HVER\n");
145
146 case MISCREG_HINTP:
147 setMiscRegNoEffect(miscReg, val);
148 if (hintp)
149 cpu->postInterrupt(IT_HINTP, 0);
150 else
151 cpu->clearInterrupt(IT_HINTP, 0);
152 break;
153
154 case MISCREG_HTBA:
155 // clear lower 7 bits on writes.
156 setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF));
157 break;
158
159 case MISCREG_QUEUE_CPU_MONDO_HEAD:
160 case MISCREG_QUEUE_CPU_MONDO_TAIL:
161 setMiscRegNoEffect(miscReg, val);
162 if (cpu_mondo_head != cpu_mondo_tail)
163 cpu->postInterrupt(IT_CPU_MONDO, 0);
164 else
165 cpu->clearInterrupt(IT_CPU_MONDO, 0);
166 break;
167 case MISCREG_QUEUE_DEV_MONDO_HEAD:
168 case MISCREG_QUEUE_DEV_MONDO_TAIL:
169 setMiscRegNoEffect(miscReg, val);
170 if (dev_mondo_head != dev_mondo_tail)
171 cpu->postInterrupt(IT_DEV_MONDO, 0);
172 else
173 cpu->clearInterrupt(IT_DEV_MONDO, 0);
174 break;
175 case MISCREG_QUEUE_RES_ERROR_HEAD:
176 case MISCREG_QUEUE_RES_ERROR_TAIL:
177 setMiscRegNoEffect(miscReg, val);
178 if (res_error_head != res_error_tail)
179 cpu->postInterrupt(IT_RES_ERROR, 0);
180 else
181 cpu->clearInterrupt(IT_RES_ERROR, 0);
182 break;
183 case MISCREG_QUEUE_NRES_ERROR_HEAD:
184 case MISCREG_QUEUE_NRES_ERROR_TAIL:
185 setMiscRegNoEffect(miscReg, val);
186 // This one doesn't have an interrupt to report to the guest OS
187 break;
188
189 case MISCREG_HSTICK_CMPR:
190 if (hSTickCompare == NULL)
191 hSTickCompare = new HSTickCompareEvent(this, tc);
192 setMiscRegNoEffect(miscReg, val);
193 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
194 cpu->deschedule(hSTickCompare);
195 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
196 cpu->instCount();
197 if (!(hstick_cmpr & ~mask(63)) && time > 0) {
198 if (hSTickCompare->scheduled())
199 cpu->deschedule(hSTickCompare);
131 }
132 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
133 break;
134
135 case MISCREG_PSTATE:
136 setMiscRegNoEffect(miscReg, val);
137
138 case MISCREG_PIL:
139 setMiscRegNoEffect(miscReg, val);
140 checkSoftInt(tc);
141 break;
142
143 case MISCREG_HVER:
144 panic("Shouldn't be writing HVER\n");
145
146 case MISCREG_HINTP:
147 setMiscRegNoEffect(miscReg, val);
148 if (hintp)
149 cpu->postInterrupt(IT_HINTP, 0);
150 else
151 cpu->clearInterrupt(IT_HINTP, 0);
152 break;
153
154 case MISCREG_HTBA:
155 // clear lower 7 bits on writes.
156 setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF));
157 break;
158
159 case MISCREG_QUEUE_CPU_MONDO_HEAD:
160 case MISCREG_QUEUE_CPU_MONDO_TAIL:
161 setMiscRegNoEffect(miscReg, val);
162 if (cpu_mondo_head != cpu_mondo_tail)
163 cpu->postInterrupt(IT_CPU_MONDO, 0);
164 else
165 cpu->clearInterrupt(IT_CPU_MONDO, 0);
166 break;
167 case MISCREG_QUEUE_DEV_MONDO_HEAD:
168 case MISCREG_QUEUE_DEV_MONDO_TAIL:
169 setMiscRegNoEffect(miscReg, val);
170 if (dev_mondo_head != dev_mondo_tail)
171 cpu->postInterrupt(IT_DEV_MONDO, 0);
172 else
173 cpu->clearInterrupt(IT_DEV_MONDO, 0);
174 break;
175 case MISCREG_QUEUE_RES_ERROR_HEAD:
176 case MISCREG_QUEUE_RES_ERROR_TAIL:
177 setMiscRegNoEffect(miscReg, val);
178 if (res_error_head != res_error_tail)
179 cpu->postInterrupt(IT_RES_ERROR, 0);
180 else
181 cpu->clearInterrupt(IT_RES_ERROR, 0);
182 break;
183 case MISCREG_QUEUE_NRES_ERROR_HEAD:
184 case MISCREG_QUEUE_NRES_ERROR_TAIL:
185 setMiscRegNoEffect(miscReg, val);
186 // This one doesn't have an interrupt to report to the guest OS
187 break;
188
189 case MISCREG_HSTICK_CMPR:
190 if (hSTickCompare == NULL)
191 hSTickCompare = new HSTickCompareEvent(this, tc);
192 setMiscRegNoEffect(miscReg, val);
193 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
194 cpu->deschedule(hSTickCompare);
195 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
196 cpu->instCount();
197 if (!(hstick_cmpr & ~mask(63)) && time > 0) {
198 if (hSTickCompare->scheduled())
199 cpu->deschedule(hSTickCompare);
200 cpu->schedule(hSTickCompare, curTick + time * cpu->ticks(1));
200 cpu->schedule(hSTickCompare, curTick() + time * cpu->ticks(1));
201 }
202 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
203 break;
204
205 case MISCREG_HPSTATE:
206 // T1000 spec says impl. dependent val must always be 1
207 setMiscRegNoEffect(miscReg, val | HPSTATE::id);
208#if FULL_SYSTEM
209 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
210 cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
211 else
212 cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
213#endif
214 break;
215 case MISCREG_HTSTATE:
216 setMiscRegNoEffect(miscReg, val);
217 break;
218
219 case MISCREG_STRAND_STS_REG:
220 if (bits(val,2,2))
221 panic("No support for setting spec_en bit\n");
222 setMiscRegNoEffect(miscReg, bits(val,0,0));
223 if (!bits(val,0,0)) {
224 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
225 // Time to go to sleep
226 tc->suspend();
227 if (tc->getKernelStats())
228 tc->getKernelStats()->quiesce();
229 }
230 break;
231
232 default:
233 panic("Invalid write to FS misc register %s\n",
234 getMiscRegName(miscReg));
235 }
236}
237
238MiscReg
239ISA::readFSReg(int miscReg, ThreadContext * tc)
240{
241 uint64_t temp;
242
243 switch (miscReg) {
244 /* Privileged registers. */
245 case MISCREG_QUEUE_CPU_MONDO_HEAD:
246 case MISCREG_QUEUE_CPU_MONDO_TAIL:
247 case MISCREG_QUEUE_DEV_MONDO_HEAD:
248 case MISCREG_QUEUE_DEV_MONDO_TAIL:
249 case MISCREG_QUEUE_RES_ERROR_HEAD:
250 case MISCREG_QUEUE_RES_ERROR_TAIL:
251 case MISCREG_QUEUE_NRES_ERROR_HEAD:
252 case MISCREG_QUEUE_NRES_ERROR_TAIL:
253 case MISCREG_SOFTINT:
254 case MISCREG_TICK_CMPR:
255 case MISCREG_STICK_CMPR:
256 case MISCREG_PIL:
257 case MISCREG_HPSTATE:
258 case MISCREG_HINTP:
259 case MISCREG_HTSTATE:
260 case MISCREG_HSTICK_CMPR:
261 return readMiscRegNoEffect(miscReg) ;
262
263 case MISCREG_HTBA:
264 return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF);
265 case MISCREG_HVER:
266 // XXX set to match Legion
267 return ULL(0x3e) << 48 |
268 ULL(0x23) << 32 |
269 ULL(0x20) << 24 |
270 // MaxGL << 16 | XXX For some reason legion doesn't set GL
271 MaxTL << 8 |
272 (NWindows -1) << 0;
273
274 case MISCREG_STRAND_STS_REG:
275 System *sys;
276 int x;
277 sys = tc->getSystemPtr();
278
279 temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative);
280 // Check that the CPU array is fully populated
281 // (by calling getNumCPus())
282 assert(sys->numContexts() > tc->contextId());
283
284 temp |= tc->contextId() << STS::shft_id;
285
286 for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) {
287 switch (sys->threadContexts[x]->status()) {
288 case ThreadContext::Active:
289 temp |= STS::st_run << (STS::shft_fsm0 -
290 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
291 break;
292 case ThreadContext::Suspended:
293 // should this be idle?
294 temp |= STS::st_idle << (STS::shft_fsm0 -
295 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
296 break;
297 case ThreadContext::Halted:
298 temp |= STS::st_halt << (STS::shft_fsm0 -
299 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
300 break;
301 default:
302 panic("What state are we in?!\n");
303 } // switch
304 } // for
305
306 return temp;
307 default:
308 panic("Invalid read to FS misc register\n");
309 }
310}
311
312void
313ISA::processTickCompare(ThreadContext *tc)
314{
315 panic("tick compare not implemented\n");
316}
317
318void
319ISA::processSTickCompare(ThreadContext *tc)
320{
321 BaseCPU *cpu = tc->getCpuPtr();
322
323 // since our microcode instructions take two cycles we need to check if
324 // we're actually at the correct cycle or we need to wait a little while
325 // more
326 int ticks;
327 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
328 cpu->instCount();
329 assert(ticks >= 0 && "stick compare missed interrupt cycle");
330
331 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
332 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
333 (stick_cmpr & mask(63)));
334 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
335 setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
336 }
337 } else {
201 }
202 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
203 break;
204
205 case MISCREG_HPSTATE:
206 // T1000 spec says impl. dependent val must always be 1
207 setMiscRegNoEffect(miscReg, val | HPSTATE::id);
208#if FULL_SYSTEM
209 if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
210 cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
211 else
212 cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
213#endif
214 break;
215 case MISCREG_HTSTATE:
216 setMiscRegNoEffect(miscReg, val);
217 break;
218
219 case MISCREG_STRAND_STS_REG:
220 if (bits(val,2,2))
221 panic("No support for setting spec_en bit\n");
222 setMiscRegNoEffect(miscReg, bits(val,0,0));
223 if (!bits(val,0,0)) {
224 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
225 // Time to go to sleep
226 tc->suspend();
227 if (tc->getKernelStats())
228 tc->getKernelStats()->quiesce();
229 }
230 break;
231
232 default:
233 panic("Invalid write to FS misc register %s\n",
234 getMiscRegName(miscReg));
235 }
236}
237
238MiscReg
239ISA::readFSReg(int miscReg, ThreadContext * tc)
240{
241 uint64_t temp;
242
243 switch (miscReg) {
244 /* Privileged registers. */
245 case MISCREG_QUEUE_CPU_MONDO_HEAD:
246 case MISCREG_QUEUE_CPU_MONDO_TAIL:
247 case MISCREG_QUEUE_DEV_MONDO_HEAD:
248 case MISCREG_QUEUE_DEV_MONDO_TAIL:
249 case MISCREG_QUEUE_RES_ERROR_HEAD:
250 case MISCREG_QUEUE_RES_ERROR_TAIL:
251 case MISCREG_QUEUE_NRES_ERROR_HEAD:
252 case MISCREG_QUEUE_NRES_ERROR_TAIL:
253 case MISCREG_SOFTINT:
254 case MISCREG_TICK_CMPR:
255 case MISCREG_STICK_CMPR:
256 case MISCREG_PIL:
257 case MISCREG_HPSTATE:
258 case MISCREG_HINTP:
259 case MISCREG_HTSTATE:
260 case MISCREG_HSTICK_CMPR:
261 return readMiscRegNoEffect(miscReg) ;
262
263 case MISCREG_HTBA:
264 return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF);
265 case MISCREG_HVER:
266 // XXX set to match Legion
267 return ULL(0x3e) << 48 |
268 ULL(0x23) << 32 |
269 ULL(0x20) << 24 |
270 // MaxGL << 16 | XXX For some reason legion doesn't set GL
271 MaxTL << 8 |
272 (NWindows -1) << 0;
273
274 case MISCREG_STRAND_STS_REG:
275 System *sys;
276 int x;
277 sys = tc->getSystemPtr();
278
279 temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative);
280 // Check that the CPU array is fully populated
281 // (by calling getNumCPus())
282 assert(sys->numContexts() > tc->contextId());
283
284 temp |= tc->contextId() << STS::shft_id;
285
286 for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) {
287 switch (sys->threadContexts[x]->status()) {
288 case ThreadContext::Active:
289 temp |= STS::st_run << (STS::shft_fsm0 -
290 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
291 break;
292 case ThreadContext::Suspended:
293 // should this be idle?
294 temp |= STS::st_idle << (STS::shft_fsm0 -
295 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
296 break;
297 case ThreadContext::Halted:
298 temp |= STS::st_halt << (STS::shft_fsm0 -
299 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
300 break;
301 default:
302 panic("What state are we in?!\n");
303 } // switch
304 } // for
305
306 return temp;
307 default:
308 panic("Invalid read to FS misc register\n");
309 }
310}
311
312void
313ISA::processTickCompare(ThreadContext *tc)
314{
315 panic("tick compare not implemented\n");
316}
317
318void
319ISA::processSTickCompare(ThreadContext *tc)
320{
321 BaseCPU *cpu = tc->getCpuPtr();
322
323 // since our microcode instructions take two cycles we need to check if
324 // we're actually at the correct cycle or we need to wait a little while
325 // more
326 int ticks;
327 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
328 cpu->instCount();
329 assert(ticks >= 0 && "stick compare missed interrupt cycle");
330
331 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
332 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
333 (stick_cmpr & mask(63)));
334 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
335 setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
336 }
337 } else {
338 cpu->schedule(sTickCompare, curTick + ticks * cpu->ticks(1));
338 cpu->schedule(sTickCompare, curTick() + ticks * cpu->ticks(1));
339 }
340}
341
342void
343ISA::processHSTickCompare(ThreadContext *tc)
344{
345 BaseCPU *cpu = tc->getCpuPtr();
346
347 // since our microcode instructions take two cycles we need to check if
348 // we're actually at the correct cycle or we need to wait a little while
349 // more
350 int ticks;
351 if ( tc->status() == ThreadContext::Halted)
352 return;
353
354 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
355 cpu->instCount();
356 assert(ticks >= 0 && "hstick compare missed interrupt cycle");
357
358 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
359 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
360 (stick_cmpr & mask(63)));
361 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
362 setMiscReg(MISCREG_HINTP, 1, tc);
363 }
364 // Need to do something to cause interrupt to happen here !!! @todo
365 } else {
339 }
340}
341
342void
343ISA::processHSTickCompare(ThreadContext *tc)
344{
345 BaseCPU *cpu = tc->getCpuPtr();
346
347 // since our microcode instructions take two cycles we need to check if
348 // we're actually at the correct cycle or we need to wait a little while
349 // more
350 int ticks;
351 if ( tc->status() == ThreadContext::Halted)
352 return;
353
354 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
355 cpu->instCount();
356 assert(ticks >= 0 && "hstick compare missed interrupt cycle");
357
358 if (ticks == 0 || tc->status() == ThreadContext::Suspended) {
359 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
360 (stick_cmpr & mask(63)));
361 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
362 setMiscReg(MISCREG_HINTP, 1, tc);
363 }
364 // Need to do something to cause interrupt to happen here !!! @todo
365 } else {
366 cpu->schedule(hSTickCompare, curTick + ticks * cpu->ticks(1));
366 cpu->schedule(hSTickCompare, curTick() + ticks * cpu->ticks(1));
367 }
368}
369
367 }
368}
369