1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/sparc/miscregfile.hh"
30#include "base/bitfield.hh"
31#include "base/trace.hh"
32#include "cpu/base.hh"
33#include "cpu/thread_context.hh"
34
35using namespace SparcISA;
36
37void
38MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
39 ThreadContext *tc)
40{
41 int64_t time;
42 switch (miscReg) {
43 /* Full system only ASRs */
44 case MISCREG_SOFTINT:
45 setReg(miscReg, val);;
| 1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/sparc/miscregfile.hh"
30#include "base/bitfield.hh"
31#include "base/trace.hh"
32#include "cpu/base.hh"
33#include "cpu/thread_context.hh"
34
35using namespace SparcISA;
36
37void
38MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
39 ThreadContext *tc)
40{
41 int64_t time;
42 switch (miscReg) {
43 /* Full system only ASRs */
44 case MISCREG_SOFTINT:
45 setReg(miscReg, val);;
|
46 if (val != 0x10000 && val != 0)
47 warn("Writing to softint not really supported, writing: %#x\n", val);
| |
48 break;
49
50 case MISCREG_SOFTINT_CLR:
51 return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
52 case MISCREG_SOFTINT_SET:
| 46 break;
47
48 case MISCREG_SOFTINT_CLR:
49 return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
50 case MISCREG_SOFTINT_SET:
|
| 51 tc->getCpuPtr()->checkInterrupts = true;
|
53 tc->getCpuPtr()->post_interrupt(soft_interrupt);
54 return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
55
56 case MISCREG_TICK_CMPR:
57 if (tickCompare == NULL)
58 tickCompare = new TickCompareEvent(this, tc);
59 setReg(miscReg, val);
60 if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
61 tickCompare->deschedule();
62 time = (tick_cmpr & mask(63)) - (tick & mask(63));
63 if (!(tick_cmpr & ~mask(63)) && time > 0)
64 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
65 panic("writing to TICK compare register %#X\n", val);
66 break;
67
68 case MISCREG_STICK_CMPR:
69 if (sTickCompare == NULL)
70 sTickCompare = new STickCompareEvent(this, tc);
71 setReg(miscReg, val);
72 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
73 sTickCompare->deschedule();
74 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
75 tc->getCpuPtr()->instCount();
76 if (!(stick_cmpr & ~mask(63)) && time > 0)
77 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
78 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
79 break;
80
81 case MISCREG_PSTATE:
| 52 tc->getCpuPtr()->post_interrupt(soft_interrupt);
53 return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
54
55 case MISCREG_TICK_CMPR:
56 if (tickCompare == NULL)
57 tickCompare = new TickCompareEvent(this, tc);
58 setReg(miscReg, val);
59 if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
60 tickCompare->deschedule();
61 time = (tick_cmpr & mask(63)) - (tick & mask(63));
62 if (!(tick_cmpr & ~mask(63)) && time > 0)
63 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
64 panic("writing to TICK compare register %#X\n", val);
65 break;
66
67 case MISCREG_STICK_CMPR:
68 if (sTickCompare == NULL)
69 sTickCompare = new STickCompareEvent(this, tc);
70 setReg(miscReg, val);
71 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
72 sTickCompare->deschedule();
73 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
74 tc->getCpuPtr()->instCount();
75 if (!(stick_cmpr & ~mask(63)) && time > 0)
76 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
77 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
78 break;
79
80 case MISCREG_PSTATE:
|
| 81 if (val & PSTATE::ie && !(pstate & PSTATE::ie)) {
82 tc->getCpuPtr()->checkInterrupts = true;
83 }
|
82 setReg(miscReg, val);
83
84 case MISCREG_PIL:
| 84 setReg(miscReg, val);
85
86 case MISCREG_PIL:
|
| 87 if (val < pil) {
88 tc->getCpuPtr()->checkInterrupts = true;
89 }
|
85 setReg(miscReg, val);
86 break;
87
88 case MISCREG_HVER:
89 panic("Shouldn't be writing HVER\n");
90
91 case MISCREG_HINTP:
92 setReg(miscReg, val);
93
94 case MISCREG_HTBA:
95 // clear lower 7 bits on writes.
96 setReg(miscReg, val & ULL(~0x7FFF));
97 break;
98
99 case MISCREG_QUEUE_CPU_MONDO_HEAD:
100 case MISCREG_QUEUE_CPU_MONDO_TAIL:
101 case MISCREG_QUEUE_DEV_MONDO_HEAD:
102 case MISCREG_QUEUE_DEV_MONDO_TAIL:
103 case MISCREG_QUEUE_RES_ERROR_HEAD:
104 case MISCREG_QUEUE_RES_ERROR_TAIL:
105 case MISCREG_QUEUE_NRES_ERROR_HEAD:
106 case MISCREG_QUEUE_NRES_ERROR_TAIL:
107 setReg(miscReg, val);
| 90 setReg(miscReg, val);
91 break;
92
93 case MISCREG_HVER:
94 panic("Shouldn't be writing HVER\n");
95
96 case MISCREG_HINTP:
97 setReg(miscReg, val);
98
99 case MISCREG_HTBA:
100 // clear lower 7 bits on writes.
101 setReg(miscReg, val & ULL(~0x7FFF));
102 break;
103
104 case MISCREG_QUEUE_CPU_MONDO_HEAD:
105 case MISCREG_QUEUE_CPU_MONDO_TAIL:
106 case MISCREG_QUEUE_DEV_MONDO_HEAD:
107 case MISCREG_QUEUE_DEV_MONDO_TAIL:
108 case MISCREG_QUEUE_RES_ERROR_HEAD:
109 case MISCREG_QUEUE_RES_ERROR_TAIL:
110 case MISCREG_QUEUE_NRES_ERROR_HEAD:
111 case MISCREG_QUEUE_NRES_ERROR_TAIL:
112 setReg(miscReg, val);
|
108 //do something to post mondo interrupt
| 113 tc->getCpuPtr()->checkInterrupts = true;
|
109 break;
110
111 case MISCREG_HSTICK_CMPR:
112 if (hSTickCompare == NULL)
113 hSTickCompare = new HSTickCompareEvent(this, tc);
114 setReg(miscReg, val);
115 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
116 hSTickCompare->deschedule();
117 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
118 tc->getCpuPtr()->instCount();
119 if (!(hstick_cmpr & ~mask(63)) && time > 0)
120 hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
121 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
122 break;
123
124 case MISCREG_HPSTATE:
125 // T1000 spec says impl. dependent val must always be 1
126 setReg(miscReg, val | HPSTATE::id);
127 break;
128 case MISCREG_HTSTATE:
129 case MISCREG_STRAND_STS_REG:
130 setReg(miscReg, val);
131 break;
132
133 default:
134 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
135 }
136}
137
138MiscReg
139MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
140{
141 switch (miscReg) {
142 /* Privileged registers. */
143 case MISCREG_QUEUE_CPU_MONDO_HEAD:
144 case MISCREG_QUEUE_CPU_MONDO_TAIL:
145 case MISCREG_QUEUE_DEV_MONDO_HEAD:
146 case MISCREG_QUEUE_DEV_MONDO_TAIL:
147 case MISCREG_QUEUE_RES_ERROR_HEAD:
148 case MISCREG_QUEUE_RES_ERROR_TAIL:
149 case MISCREG_QUEUE_NRES_ERROR_HEAD:
150 case MISCREG_QUEUE_NRES_ERROR_TAIL:
151 case MISCREG_SOFTINT:
152 case MISCREG_TICK_CMPR:
153 case MISCREG_STICK_CMPR:
154 case MISCREG_PIL:
155 case MISCREG_HPSTATE:
156 case MISCREG_HINTP:
157 case MISCREG_HTSTATE:
158 case MISCREG_STRAND_STS_REG:
159 case MISCREG_HSTICK_CMPR:
160 return readReg(miscReg) ;
161
162 case MISCREG_HTBA:
163 return readReg(miscReg) & ULL(~0x7FFF);
164 case MISCREG_HVER:
165 return NWindows | MaxTL << 8 | MaxGL << 16;
166
167 default:
168 panic("Invalid read to FS misc register\n");
169 }
170}
171/*
172 In Niagra STICK==TICK so this isn't needed
173 case MISCREG_STICK:
174 SparcSystem *sys;
175 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
176 assert(sys != NULL);
177 return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
178*/
179
180
181
182void
183MiscRegFile::processTickCompare(ThreadContext *tc)
184{
185 panic("tick compare not implemented\n");
186}
187
188void
189MiscRegFile::processSTickCompare(ThreadContext *tc)
190{
191 // since our microcode instructions take two cycles we need to check if
192 // we're actually at the correct cycle or we need to wait a little while
193 // more
194 int ticks;
195 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
196 tc->getCpuPtr()->instCount();
197 assert(ticks >= 0 && "stick compare missed interrupt cycle");
198
199 if (ticks == 0) {
200 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
201 (stick_cmpr & mask(63)));
202 if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
203 tc->getCpuPtr()->post_interrupt(soft_interrupt);
| 114 break;
115
116 case MISCREG_HSTICK_CMPR:
117 if (hSTickCompare == NULL)
118 hSTickCompare = new HSTickCompareEvent(this, tc);
119 setReg(miscReg, val);
120 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
121 hSTickCompare->deschedule();
122 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
123 tc->getCpuPtr()->instCount();
124 if (!(hstick_cmpr & ~mask(63)) && time > 0)
125 hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
126 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
127 break;
128
129 case MISCREG_HPSTATE:
130 // T1000 spec says impl. dependent val must always be 1
131 setReg(miscReg, val | HPSTATE::id);
132 break;
133 case MISCREG_HTSTATE:
134 case MISCREG_STRAND_STS_REG:
135 setReg(miscReg, val);
136 break;
137
138 default:
139 panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
140 }
141}
142
143MiscReg
144MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
145{
146 switch (miscReg) {
147 /* Privileged registers. */
148 case MISCREG_QUEUE_CPU_MONDO_HEAD:
149 case MISCREG_QUEUE_CPU_MONDO_TAIL:
150 case MISCREG_QUEUE_DEV_MONDO_HEAD:
151 case MISCREG_QUEUE_DEV_MONDO_TAIL:
152 case MISCREG_QUEUE_RES_ERROR_HEAD:
153 case MISCREG_QUEUE_RES_ERROR_TAIL:
154 case MISCREG_QUEUE_NRES_ERROR_HEAD:
155 case MISCREG_QUEUE_NRES_ERROR_TAIL:
156 case MISCREG_SOFTINT:
157 case MISCREG_TICK_CMPR:
158 case MISCREG_STICK_CMPR:
159 case MISCREG_PIL:
160 case MISCREG_HPSTATE:
161 case MISCREG_HINTP:
162 case MISCREG_HTSTATE:
163 case MISCREG_STRAND_STS_REG:
164 case MISCREG_HSTICK_CMPR:
165 return readReg(miscReg) ;
166
167 case MISCREG_HTBA:
168 return readReg(miscReg) & ULL(~0x7FFF);
169 case MISCREG_HVER:
170 return NWindows | MaxTL << 8 | MaxGL << 16;
171
172 default:
173 panic("Invalid read to FS misc register\n");
174 }
175}
176/*
177 In Niagra STICK==TICK so this isn't needed
178 case MISCREG_STICK:
179 SparcSystem *sys;
180 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
181 assert(sys != NULL);
182 return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
183*/
184
185
186
187void
188MiscRegFile::processTickCompare(ThreadContext *tc)
189{
190 panic("tick compare not implemented\n");
191}
192
193void
194MiscRegFile::processSTickCompare(ThreadContext *tc)
195{
196 // since our microcode instructions take two cycles we need to check if
197 // we're actually at the correct cycle or we need to wait a little while
198 // more
199 int ticks;
200 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
201 tc->getCpuPtr()->instCount();
202 assert(ticks >= 0 && "stick compare missed interrupt cycle");
203
204 if (ticks == 0) {
205 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
206 (stick_cmpr & mask(63)));
207 if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
208 tc->getCpuPtr()->post_interrupt(soft_interrupt);
|
| 209 tc->getCpuPtr()->checkInterrupts = true;
|
204 setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
205 }
206 } else
207 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
208}
209
210void
211MiscRegFile::processHSTickCompare(ThreadContext *tc)
212{
213 // since our microcode instructions take two cycles we need to check if
214 // we're actually at the correct cycle or we need to wait a little while
215 // more
216 int ticks;
217 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
218 tc->getCpuPtr()->instCount();
219 assert(ticks >= 0 && "hstick compare missed interrupt cycle");
220
221 if (ticks == 0) {
222 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
223 (stick_cmpr & mask(63)));
224 if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
225 setRegWithEffect(MISCREG_HINTP, 1, tc);
226 tc->getCpuPtr()->post_interrupt(hstick_match);
| 210 setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
211 }
212 } else
213 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
214}
215
216void
217MiscRegFile::processHSTickCompare(ThreadContext *tc)
218{
219 // since our microcode instructions take two cycles we need to check if
220 // we're actually at the correct cycle or we need to wait a little while
221 // more
222 int ticks;
223 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
224 tc->getCpuPtr()->instCount();
225 assert(ticks >= 0 && "hstick compare missed interrupt cycle");
226
227 if (ticks == 0) {
228 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
229 (stick_cmpr & mask(63)));
230 if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
231 setRegWithEffect(MISCREG_HINTP, 1, tc);
232 tc->getCpuPtr()->post_interrupt(hstick_match);
|
| 233 tc->getCpuPtr()->checkInterrupts = true;
|
227 }
228 // Need to do something to cause interrupt to happen here !!! @todo
229 } else
230 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
231}
232
| 234 }
235 // Need to do something to cause interrupt to happen here !!! @todo
236 } else
237 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
238}
239
|