1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30
| 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30
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31#include "arch/sparc/regfile.hh"
| 31#include "arch/sparc/miscregfile.hh" 32#include "base/bitfield.hh" 33#include "base/trace.hh" 34#include "cpu/base.hh" 35#include "cpu/thread_context.hh"
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32
| 36
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33Fault 34SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
| 37using namespace SparcISA; 38 39void 40MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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35 ThreadContext *tc) 36{ 37 int64_t time;
| 41 ThreadContext *tc) 42{ 43 int64_t time;
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38 SparcSystem *sys;
| 44 int oldLevel, newLevel;
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39 switch (miscReg) { 40 /* Full system only ASRs */ 41 case MISCREG_SOFTINT:
| 45 switch (miscReg) { 46 /* Full system only ASRs */ 47 case MISCREG_SOFTINT:
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42 if (isNonPriv()) 43 return new PrivilegedOpcode;
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44 // Check if we are going to interrupt because of something
| 48 // Check if we are going to interrupt because of something
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45 int oldLevel = InterruptLevel(softint); 46 int newLevel = InterruptLevel(val);
| 49 oldLevel = InterruptLevel(softint); 50 newLevel = InterruptLevel(val);
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47 setReg(miscReg, val); 48 if (newLevel > oldLevel) 49 ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 50 //tc->getCpuPtr()->checkInterrupts = true;
| 51 setReg(miscReg, val); 52 if (newLevel > oldLevel) 53 ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 54 //tc->getCpuPtr()->checkInterrupts = true;
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51 return NoFault;
| 55 panic("SOFTINT not implemented\n"); 56 break;
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52 53 case MISCREG_SOFTINT_CLR: 54 return setRegWithEffect(miscReg, ~val & softint, tc); 55 case MISCREG_SOFTINT_SET: 56 return setRegWithEffect(miscReg, val | softint, tc); 57 58 case MISCREG_TICK_CMPR:
| 57 58 case MISCREG_SOFTINT_CLR: 59 return setRegWithEffect(miscReg, ~val & softint, tc); 60 case MISCREG_SOFTINT_SET: 61 return setRegWithEffect(miscReg, val | softint, tc); 62 63 case MISCREG_TICK_CMPR:
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59 if (isNonPriv()) 60 return new PrivilegedOpcode;
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61 if (tickCompare == NULL) 62 tickCompare = new TickCompareEvent(this, tc); 63 setReg(miscReg, val);
| 64 if (tickCompare == NULL) 65 tickCompare = new TickCompareEvent(this, tc); 66 setReg(miscReg, val);
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64 if (tick_cmprFields.int_dis && tickCompare.scheduled()) 65 tickCompare.deschedule(); 66 time = tick_cmprFields.tick_cmpr - tickFields.counter; 67 if (!tick_cmprFields.int_dis && time > 0) 68 tickCompare.schedule(time * tc->getCpuPtr()->cycles(1)); 69 return NoFault;
| 67 if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) 68 tickCompare->deschedule(); 69 time = (tick_cmpr & mask(63)) - (tick & mask(63)); 70 if (!(tick_cmpr & ~mask(63)) && time > 0) 71 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 72 break;
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70
| 73
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71 case MISCREG_STICK: 72 if (isNonPriv()) 73 return new PrivilegedOpcode; 74 if (isPriv()) 75 return new PrivilegedAction; 76 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 77 assert(sys != NULL); 78 sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; 79 stickFields.npt = val & Bit64 ? 1 : 0; 80 return NoFault; 81
| |
82 case MISCREG_STICK_CMPR:
| 74 case MISCREG_STICK_CMPR:
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83 if (isNonPriv()) 84 return new PrivilegedOpcode;
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85 if (sTickCompare == NULL) 86 sTickCompare = new STickCompareEvent(this, tc);
| 75 if (sTickCompare == NULL) 76 sTickCompare = new STickCompareEvent(this, tc);
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87 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 88 assert(sys != NULL);
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89 setReg(miscReg, val);
| 77 setReg(miscReg, val);
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90 if (stick_cmprFields.int_dis && sTickCompare.scheduled()) 91 sTickCompare.deschedule(); 92 time = stick_cmprFields.tick_cmpr - sys->sysTick; 93 if (!stick_cmprFields.int_dis && time > 0) 94 sTickCompare.schedule(time * Clock::Int::ns); 95 return NoFault;
| 78 if ((stick_cmpr & mask(63)) && sTickCompare->scheduled()) 79 sTickCompare->deschedule(); 80 time = (stick_cmpr & mask(63)) - (stick & mask(63)); 81 if (!(stick_cmpr & ~mask(63)) && time > 0) 82 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 83 break;
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96
| 84
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97 /* Fullsystem only Priv registers. */
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98 case MISCREG_PIL:
| 85 case MISCREG_PIL:
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99 if (FULL_SYSTEM) { 100 setReg(miscReg, val); 101 //tc->getCpuPtr()->checkInterrupts; 102 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 103 return NoFault; 104 } else 105 panic("PIL not implemented for syscall emulation\n"); 106 107 /* Hyper privileged registers */ 108 case MISCREG_HPSTATE: 109 case MISCREG_HINTP:
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110 setReg(miscReg, val);
| 86 setReg(miscReg, val);
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111 return NoFault; 112 case MISCREG_HTSTATE: 113 if (tl == 0) 114 return new IllegalInstruction; 115 setReg(miscReg, val); 116 return NoFault;
| 87 //tc->getCpuPtr()->checkInterrupts; 88 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 89 panic("PIL not implemented\n"); 90 break;
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117
| 91
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| 92 case MISCREG_HVER: 93 panic("Shouldn't be writing HVER\n"); 94
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118 case MISCREG_HTBA: 119 // clear lower 7 bits on writes. 120 setReg(miscReg, val & ULL(~0x7FFF));
| 95 case MISCREG_HTBA: 96 // clear lower 7 bits on writes. 97 setReg(miscReg, val & ULL(~0x7FFF));
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121 return NoFault;
| 98 break;
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122
| 99
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123 case MISCREG_STRAND_STS_REG: 124 setReg(miscReg, strandStatusReg); 125 return NoFault;
| |
126 case MISCREG_HSTICK_CMPR:
| 100 case MISCREG_HSTICK_CMPR:
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127 if (isNonPriv()) 128 return new PrivilegedOpcode;
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129 if (hSTickCompare == NULL) 130 hSTickCompare = new HSTickCompareEvent(this, tc);
| 101 if (hSTickCompare == NULL) 102 hSTickCompare = new HSTickCompareEvent(this, tc);
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131 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 132 assert(sys != NULL);
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133 setReg(miscReg, val);
| 103 setReg(miscReg, val);
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134 if (hstick_cmprFields.int_dis && hSTickCompare.scheduled()) 135 hSTickCompare.deschedule(); 136 int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick; 137 if (!hstick_cmprFields.int_dis && time > 0) 138 hSTickCompare.schedule(time * Clock::Int::ns); 139 return NoFault;
| 104 if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled()) 105 hSTickCompare->deschedule(); 106 time = (hstick_cmpr & mask(63)) - (stick & mask(63)); 107 if (!(hstick_cmpr & ~mask(63)) && time > 0) 108 hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1)); 109 break; 110 111 case MISCREG_HPSTATE: 112 case MISCREG_HTSTATE: 113 case MISCREG_STRAND_STS_REG: 114 setReg(miscReg, val); 115 break; 116
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140 default:
| 117 default:
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141 return new IllegalInstruction;
| 118 panic("Invalid write to FS misc register\n");
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142 } 143} 144 145MiscReg
| 119 } 120} 121 122MiscReg
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146MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc)
| 123MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
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147{ 148 switch (miscReg) { 149 150 /* Privileged registers. */ 151 case MISCREG_SOFTINT:
| 124{ 125 switch (miscReg) { 126 127 /* Privileged registers. */ 128 case MISCREG_SOFTINT:
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152 if (isNonPriv()) { 153 fault = new PrivilegedOpcode; 154 return 0; 155 } 156 return readReg(miscReg);
| |
157 case MISCREG_TICK_CMPR:
| 129 case MISCREG_TICK_CMPR:
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158 if (isNonPriv()) { 159 fault = new PrivilegedOpcode; 160 return 0; 161 } 162 return readReg(miscReg); 163 case MISCREG_STICK: 164 SparcSystem *sys; 165 if (stickFields.npt && !isNonPriv()) { 166 fault = new PrivilegedAction; 167 return 0; 168 } 169 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 170 assert(sys != NULL); 171 return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
| |
172 case MISCREG_STICK_CMPR:
| 130 case MISCREG_STICK_CMPR:
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173 if (isNonPriv()) { 174 fault = new PrivilegedOpcode; 175 return 0; 176 } 177 return readReg(miscReg); 178 179 180 /* Hyper privileged registers */
| 131 case MISCREG_PIL:
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181 case MISCREG_HPSTATE: 182 case MISCREG_HINTP:
| 132 case MISCREG_HPSTATE: 133 case MISCREG_HINTP:
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183 return readReg(miscReg);
| |
184 case MISCREG_HTSTATE:
| 134 case MISCREG_HTSTATE:
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185 if (tl == 0) { 186 fault = new IllegalInstruction; 187 return 0; 188 } 189 return readReg(miscReg);
| 135 case MISCREG_STRAND_STS_REG: 136 case MISCREG_HSTICK_CMPR: 137 return readReg(miscReg) ;
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190 191 case MISCREG_HTBA: 192 return readReg(miscReg) & ULL(~0x7FFF); 193 case MISCREG_HVER: 194 return NWindows | MaxTL << 8 | MaxGL << 16;
| 138 139 case MISCREG_HTBA: 140 return readReg(miscReg) & ULL(~0x7FFF); 141 case MISCREG_HVER: 142 return NWindows | MaxTL << 8 | MaxGL << 16;
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195 case MISCREG_STRAND_STS_REG: 196 return strandStatusReg; 197 case MISCREG_HSTICK_CMPR: 198 return hstick_cmpr;
| |
199 200 default:
| 143 144 default:
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201 fault = new IllegalInstruction; 202 return 0;
| 145 panic("Invalid read to FS misc register\n");
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203 } 204}
| 146 } 147}
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| 148/* 149 In Niagra STICK==TICK so this isn't needed 150 case MISCREG_STICK: 151 SparcSystem *sys; 152 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr()); 153 assert(sys != NULL); 154 return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63))); 155*/
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205
| 156
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| 157 158
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206void 207MiscRegFile::processTickCompare(ThreadContext *tc) 208{ 209 panic("tick compare not implemented\n"); 210} 211 212void 213MiscRegFile::processSTickCompare(ThreadContext *tc) 214{ 215 panic("tick compare not implemented\n"); 216} 217 218void 219MiscRegFile::processHSTickCompare(ThreadContext *tc) 220{ 221 panic("tick compare not implemented\n"); 222} 223
| 159void 160MiscRegFile::processTickCompare(ThreadContext *tc) 161{ 162 panic("tick compare not implemented\n"); 163} 164 165void 166MiscRegFile::processSTickCompare(ThreadContext *tc) 167{ 168 panic("tick compare not implemented\n"); 169} 170 171void 172MiscRegFile::processHSTickCompare(ThreadContext *tc) 173{ 174 panic("tick compare not implemented\n"); 175} 176
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224}; // namespace SparcISA
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