ua2005.cc (13582:989577bf6abc) ua2005.cc (13583:f7482392b097)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/sparc/isa.hh"
30#include "arch/sparc/kernel_stats.hh"
31#include "arch/sparc/registers.hh"
32#include "base/bitfield.hh"
33#include "base/trace.hh"
34#include "cpu/base.hh"
35#include "cpu/thread_context.hh"
36#include "debug/Quiesce.hh"
37#include "debug/Timer.hh"
38#include "sim/full_system.hh"
39#include "sim/system.hh"
40
41using namespace SparcISA;
42using namespace std;
43
44
45void
46ISA::checkSoftInt(ThreadContext *tc)
47{
48 BaseCPU *cpu = tc->getCpuPtr();
49
50 // If PIL < 14, copy over the tm and sm bits
51 if (pil < 14 && softint & 0x10000)
52 cpu->postInterrupt(0, IT_SOFT_INT, 16);
53 else
54 cpu->clearInterrupt(0, IT_SOFT_INT, 16);
55 if (pil < 14 && softint & 0x1)
56 cpu->postInterrupt(0, IT_SOFT_INT, 0);
57 else
58 cpu->clearInterrupt(0, IT_SOFT_INT, 0);
59
60 // Copy over any of the other bits that are set
61 for (int bit = 15; bit > 0; --bit) {
62 if (1 << bit & softint && bit > pil)
63 cpu->postInterrupt(0, IT_SOFT_INT, bit);
64 else
65 cpu->clearInterrupt(0, IT_SOFT_INT, bit);
66 }
67}
68
69// These functions map register indices to names
70static inline string
71getMiscRegName(RegIndex index)
72{
73 static string miscRegName[NumMiscRegs] =
74 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
75 "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
76 "stick", "stick_cmpr",
77 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
78 "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
79 "wstate",*/ "gl",
80 "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
81 "hstick_cmpr",
82 "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
83 "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
84 "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
85 "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
86 "nresErrorHead", "nresErrorTail", "TlbData" };
87 return miscRegName[index];
88}
89
90void
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/sparc/isa.hh"
30#include "arch/sparc/kernel_stats.hh"
31#include "arch/sparc/registers.hh"
32#include "base/bitfield.hh"
33#include "base/trace.hh"
34#include "cpu/base.hh"
35#include "cpu/thread_context.hh"
36#include "debug/Quiesce.hh"
37#include "debug/Timer.hh"
38#include "sim/full_system.hh"
39#include "sim/system.hh"
40
41using namespace SparcISA;
42using namespace std;
43
44
45void
46ISA::checkSoftInt(ThreadContext *tc)
47{
48 BaseCPU *cpu = tc->getCpuPtr();
49
50 // If PIL < 14, copy over the tm and sm bits
51 if (pil < 14 && softint & 0x10000)
52 cpu->postInterrupt(0, IT_SOFT_INT, 16);
53 else
54 cpu->clearInterrupt(0, IT_SOFT_INT, 16);
55 if (pil < 14 && softint & 0x1)
56 cpu->postInterrupt(0, IT_SOFT_INT, 0);
57 else
58 cpu->clearInterrupt(0, IT_SOFT_INT, 0);
59
60 // Copy over any of the other bits that are set
61 for (int bit = 15; bit > 0; --bit) {
62 if (1 << bit & softint && bit > pil)
63 cpu->postInterrupt(0, IT_SOFT_INT, bit);
64 else
65 cpu->clearInterrupt(0, IT_SOFT_INT, bit);
66 }
67}
68
69// These functions map register indices to names
70static inline string
71getMiscRegName(RegIndex index)
72{
73 static string miscRegName[NumMiscRegs] =
74 {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
75 "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
76 "stick", "stick_cmpr",
77 "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
78 "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
79 "wstate",*/ "gl",
80 "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
81 "hstick_cmpr",
82 "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
83 "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
84 "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
85 "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
86 "nresErrorHead", "nresErrorTail", "TlbData" };
87 return miscRegName[index];
88}
89
90void
91ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc)
91ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc)
92{
93 BaseCPU *cpu = tc->getCpuPtr();
94
95 int64_t time;
96 switch (miscReg) {
97 /* Full system only ASRs */
98 case MISCREG_SOFTINT:
99 setMiscRegNoEffect(miscReg, val);;
100 checkSoftInt(tc);
101 break;
102 case MISCREG_SOFTINT_CLR:
103 return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc);
104 case MISCREG_SOFTINT_SET:
105 return setMiscReg(MISCREG_SOFTINT, val | softint, tc);
106
107 case MISCREG_TICK_CMPR:
108 if (tickCompare == NULL)
109 tickCompare = new TickCompareEvent(this, tc);
110 setMiscRegNoEffect(miscReg, val);
111 if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
112 cpu->deschedule(tickCompare);
113 time = (tick_cmpr & mask(63)) - (tick & mask(63));
114 if (!(tick_cmpr & ~mask(63)) && time > 0) {
115 if (tickCompare->scheduled())
116 cpu->deschedule(tickCompare);
117 cpu->schedule(tickCompare, cpu->clockEdge(Cycles(time)));
118 }
119 DPRINTF(Timer, "writing to TICK compare register value %#X\n", val);
120 break;
121
122 case MISCREG_STICK_CMPR:
123 if (sTickCompare == NULL)
124 sTickCompare = new STickCompareEvent(this, tc);
125 setMiscRegNoEffect(miscReg, val);
126 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
127 cpu->deschedule(sTickCompare);
128 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
129 cpu->instCount();
130 if (!(stick_cmpr & ~mask(63)) && time > 0) {
131 if (sTickCompare->scheduled())
132 cpu->deschedule(sTickCompare);
133 cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(time)));
134 }
135 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
136 break;
137
138 case MISCREG_PSTATE:
139 setMiscRegNoEffect(miscReg, val);
140 break;
141
142 case MISCREG_PIL:
143 setMiscRegNoEffect(miscReg, val);
144 checkSoftInt(tc);
145 break;
146
147 case MISCREG_HVER:
148 panic("Shouldn't be writing HVER\n");
149
150 case MISCREG_HINTP:
151 setMiscRegNoEffect(miscReg, val);
152 if (hintp)
153 cpu->postInterrupt(0, IT_HINTP, 0);
154 else
155 cpu->clearInterrupt(0, IT_HINTP, 0);
156 break;
157
158 case MISCREG_HTBA:
159 // clear lower 7 bits on writes.
160 setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF));
161 break;
162
163 case MISCREG_QUEUE_CPU_MONDO_HEAD:
164 case MISCREG_QUEUE_CPU_MONDO_TAIL:
165 setMiscRegNoEffect(miscReg, val);
166 if (cpu_mondo_head != cpu_mondo_tail)
167 cpu->postInterrupt(0, IT_CPU_MONDO, 0);
168 else
169 cpu->clearInterrupt(0, IT_CPU_MONDO, 0);
170 break;
171 case MISCREG_QUEUE_DEV_MONDO_HEAD:
172 case MISCREG_QUEUE_DEV_MONDO_TAIL:
173 setMiscRegNoEffect(miscReg, val);
174 if (dev_mondo_head != dev_mondo_tail)
175 cpu->postInterrupt(0, IT_DEV_MONDO, 0);
176 else
177 cpu->clearInterrupt(0, IT_DEV_MONDO, 0);
178 break;
179 case MISCREG_QUEUE_RES_ERROR_HEAD:
180 case MISCREG_QUEUE_RES_ERROR_TAIL:
181 setMiscRegNoEffect(miscReg, val);
182 if (res_error_head != res_error_tail)
183 cpu->postInterrupt(0, IT_RES_ERROR, 0);
184 else
185 cpu->clearInterrupt(0, IT_RES_ERROR, 0);
186 break;
187 case MISCREG_QUEUE_NRES_ERROR_HEAD:
188 case MISCREG_QUEUE_NRES_ERROR_TAIL:
189 setMiscRegNoEffect(miscReg, val);
190 // This one doesn't have an interrupt to report to the guest OS
191 break;
192
193 case MISCREG_HSTICK_CMPR:
194 if (hSTickCompare == NULL)
195 hSTickCompare = new HSTickCompareEvent(this, tc);
196 setMiscRegNoEffect(miscReg, val);
197 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
198 cpu->deschedule(hSTickCompare);
199 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
200 cpu->instCount();
201 if (!(hstick_cmpr & ~mask(63)) && time > 0) {
202 if (hSTickCompare->scheduled())
203 cpu->deschedule(hSTickCompare);
204 cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(time)));
205 }
206 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
207 break;
208
209 case MISCREG_HPSTATE:
210 {
211 HPSTATE newVal = val;
212 newVal.id = 1;
213 // T1000 spec says impl. dependent val must always be 1
214 setMiscRegNoEffect(miscReg, newVal);
215 newVal = hpstate;
216 if (newVal.tlz && tl == 0 && !newVal.hpriv)
217 cpu->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
218 else
219 cpu->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
220 break;
221 }
222 case MISCREG_HTSTATE:
223 setMiscRegNoEffect(miscReg, val);
224 break;
225
226 case MISCREG_STRAND_STS_REG:
227 if (bits(val,2,2))
228 panic("No support for setting spec_en bit\n");
229 setMiscRegNoEffect(miscReg, bits(val,0,0));
230 if (!bits(val,0,0)) {
231 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
232 // Time to go to sleep
233 tc->suspend();
234 if (FullSystem && tc->getKernelStats())
235 tc->getKernelStats()->quiesce();
236 }
237 break;
238
239 default:
240 panic("Invalid write to FS misc register %s\n",
241 getMiscRegName(miscReg));
242 }
243}
244
92{
93 BaseCPU *cpu = tc->getCpuPtr();
94
95 int64_t time;
96 switch (miscReg) {
97 /* Full system only ASRs */
98 case MISCREG_SOFTINT:
99 setMiscRegNoEffect(miscReg, val);;
100 checkSoftInt(tc);
101 break;
102 case MISCREG_SOFTINT_CLR:
103 return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc);
104 case MISCREG_SOFTINT_SET:
105 return setMiscReg(MISCREG_SOFTINT, val | softint, tc);
106
107 case MISCREG_TICK_CMPR:
108 if (tickCompare == NULL)
109 tickCompare = new TickCompareEvent(this, tc);
110 setMiscRegNoEffect(miscReg, val);
111 if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled())
112 cpu->deschedule(tickCompare);
113 time = (tick_cmpr & mask(63)) - (tick & mask(63));
114 if (!(tick_cmpr & ~mask(63)) && time > 0) {
115 if (tickCompare->scheduled())
116 cpu->deschedule(tickCompare);
117 cpu->schedule(tickCompare, cpu->clockEdge(Cycles(time)));
118 }
119 DPRINTF(Timer, "writing to TICK compare register value %#X\n", val);
120 break;
121
122 case MISCREG_STICK_CMPR:
123 if (sTickCompare == NULL)
124 sTickCompare = new STickCompareEvent(this, tc);
125 setMiscRegNoEffect(miscReg, val);
126 if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
127 cpu->deschedule(sTickCompare);
128 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
129 cpu->instCount();
130 if (!(stick_cmpr & ~mask(63)) && time > 0) {
131 if (sTickCompare->scheduled())
132 cpu->deschedule(sTickCompare);
133 cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(time)));
134 }
135 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
136 break;
137
138 case MISCREG_PSTATE:
139 setMiscRegNoEffect(miscReg, val);
140 break;
141
142 case MISCREG_PIL:
143 setMiscRegNoEffect(miscReg, val);
144 checkSoftInt(tc);
145 break;
146
147 case MISCREG_HVER:
148 panic("Shouldn't be writing HVER\n");
149
150 case MISCREG_HINTP:
151 setMiscRegNoEffect(miscReg, val);
152 if (hintp)
153 cpu->postInterrupt(0, IT_HINTP, 0);
154 else
155 cpu->clearInterrupt(0, IT_HINTP, 0);
156 break;
157
158 case MISCREG_HTBA:
159 // clear lower 7 bits on writes.
160 setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF));
161 break;
162
163 case MISCREG_QUEUE_CPU_MONDO_HEAD:
164 case MISCREG_QUEUE_CPU_MONDO_TAIL:
165 setMiscRegNoEffect(miscReg, val);
166 if (cpu_mondo_head != cpu_mondo_tail)
167 cpu->postInterrupt(0, IT_CPU_MONDO, 0);
168 else
169 cpu->clearInterrupt(0, IT_CPU_MONDO, 0);
170 break;
171 case MISCREG_QUEUE_DEV_MONDO_HEAD:
172 case MISCREG_QUEUE_DEV_MONDO_TAIL:
173 setMiscRegNoEffect(miscReg, val);
174 if (dev_mondo_head != dev_mondo_tail)
175 cpu->postInterrupt(0, IT_DEV_MONDO, 0);
176 else
177 cpu->clearInterrupt(0, IT_DEV_MONDO, 0);
178 break;
179 case MISCREG_QUEUE_RES_ERROR_HEAD:
180 case MISCREG_QUEUE_RES_ERROR_TAIL:
181 setMiscRegNoEffect(miscReg, val);
182 if (res_error_head != res_error_tail)
183 cpu->postInterrupt(0, IT_RES_ERROR, 0);
184 else
185 cpu->clearInterrupt(0, IT_RES_ERROR, 0);
186 break;
187 case MISCREG_QUEUE_NRES_ERROR_HEAD:
188 case MISCREG_QUEUE_NRES_ERROR_TAIL:
189 setMiscRegNoEffect(miscReg, val);
190 // This one doesn't have an interrupt to report to the guest OS
191 break;
192
193 case MISCREG_HSTICK_CMPR:
194 if (hSTickCompare == NULL)
195 hSTickCompare = new HSTickCompareEvent(this, tc);
196 setMiscRegNoEffect(miscReg, val);
197 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
198 cpu->deschedule(hSTickCompare);
199 time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
200 cpu->instCount();
201 if (!(hstick_cmpr & ~mask(63)) && time > 0) {
202 if (hSTickCompare->scheduled())
203 cpu->deschedule(hSTickCompare);
204 cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(time)));
205 }
206 DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
207 break;
208
209 case MISCREG_HPSTATE:
210 {
211 HPSTATE newVal = val;
212 newVal.id = 1;
213 // T1000 spec says impl. dependent val must always be 1
214 setMiscRegNoEffect(miscReg, newVal);
215 newVal = hpstate;
216 if (newVal.tlz && tl == 0 && !newVal.hpriv)
217 cpu->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
218 else
219 cpu->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
220 break;
221 }
222 case MISCREG_HTSTATE:
223 setMiscRegNoEffect(miscReg, val);
224 break;
225
226 case MISCREG_STRAND_STS_REG:
227 if (bits(val,2,2))
228 panic("No support for setting spec_en bit\n");
229 setMiscRegNoEffect(miscReg, bits(val,0,0));
230 if (!bits(val,0,0)) {
231 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
232 // Time to go to sleep
233 tc->suspend();
234 if (FullSystem && tc->getKernelStats())
235 tc->getKernelStats()->quiesce();
236 }
237 break;
238
239 default:
240 panic("Invalid write to FS misc register %s\n",
241 getMiscRegName(miscReg));
242 }
243}
244
245MiscReg
245RegVal
246ISA::readFSReg(int miscReg, ThreadContext * tc)
247{
248 uint64_t temp;
249
250 switch (miscReg) {
251 /* Privileged registers. */
252 case MISCREG_QUEUE_CPU_MONDO_HEAD:
253 case MISCREG_QUEUE_CPU_MONDO_TAIL:
254 case MISCREG_QUEUE_DEV_MONDO_HEAD:
255 case MISCREG_QUEUE_DEV_MONDO_TAIL:
256 case MISCREG_QUEUE_RES_ERROR_HEAD:
257 case MISCREG_QUEUE_RES_ERROR_TAIL:
258 case MISCREG_QUEUE_NRES_ERROR_HEAD:
259 case MISCREG_QUEUE_NRES_ERROR_TAIL:
260 case MISCREG_SOFTINT:
261 case MISCREG_TICK_CMPR:
262 case MISCREG_STICK_CMPR:
263 case MISCREG_PIL:
264 case MISCREG_HPSTATE:
265 case MISCREG_HINTP:
266 case MISCREG_HTSTATE:
267 case MISCREG_HSTICK_CMPR:
268 return readMiscRegNoEffect(miscReg) ;
269
270 case MISCREG_HTBA:
271 return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF);
272 case MISCREG_HVER:
273 // XXX set to match Legion
274 return ULL(0x3e) << 48 |
275 ULL(0x23) << 32 |
276 ULL(0x20) << 24 |
277 // MaxGL << 16 | XXX For some reason legion doesn't set GL
278 MaxTL << 8 |
279 (NWindows -1) << 0;
280
281 case MISCREG_STRAND_STS_REG:
282 System *sys;
283 int x;
284 sys = tc->getSystemPtr();
285
286 temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative);
287 // Check that the CPU array is fully populated
288 // (by calling getNumCPus())
289 assert(sys->numContexts() > tc->contextId());
290
291 temp |= tc->contextId() << STS::shft_id;
292
293 for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) {
294 switch (sys->threadContexts[x]->status()) {
295 case ThreadContext::Active:
296 temp |= STS::st_run << (STS::shft_fsm0 -
297 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
298 break;
299 case ThreadContext::Suspended:
300 // should this be idle?
301 temp |= STS::st_idle << (STS::shft_fsm0 -
302 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
303 break;
304 case ThreadContext::Halted:
305 temp |= STS::st_halt << (STS::shft_fsm0 -
306 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
307 break;
308 default:
309 panic("What state are we in?!\n");
310 } // switch
311 } // for
312
313 return temp;
314 default:
315 panic("Invalid read to FS misc register\n");
316 }
317}
318
319void
320ISA::processTickCompare(ThreadContext *tc)
321{
322 panic("tick compare not implemented\n");
323}
324
325void
326ISA::processSTickCompare(ThreadContext *tc)
327{
328 BaseCPU *cpu = tc->getCpuPtr();
329
330 // since our microcode instructions take two cycles we need to check if
331 // we're actually at the correct cycle or we need to wait a little while
332 // more
333 int delay;
334 delay = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
335 cpu->instCount();
336 assert(delay >= 0 && "stick compare missed interrupt cycle");
337
338 if (delay == 0 || tc->status() == ThreadContext::Suspended) {
339 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
340 (stick_cmpr & mask(63)));
341 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
342 setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
343 }
344 } else {
345 cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(delay)));
346 }
347}
348
349void
350ISA::processHSTickCompare(ThreadContext *tc)
351{
352 BaseCPU *cpu = tc->getCpuPtr();
353
354 // since our microcode instructions take two cycles we need to check if
355 // we're actually at the correct cycle or we need to wait a little while
356 // more
357 int delay;
358 if ( tc->status() == ThreadContext::Halted)
359 return;
360
361 delay = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
362 cpu->instCount();
363 assert(delay >= 0 && "hstick compare missed interrupt cycle");
364
365 if (delay == 0 || tc->status() == ThreadContext::Suspended) {
366 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
367 (stick_cmpr & mask(63)));
368 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
369 setMiscReg(MISCREG_HINTP, 1, tc);
370 }
371 // Need to do something to cause interrupt to happen here !!! @todo
372 } else {
373 cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(delay)));
374 }
375}
376
246ISA::readFSReg(int miscReg, ThreadContext * tc)
247{
248 uint64_t temp;
249
250 switch (miscReg) {
251 /* Privileged registers. */
252 case MISCREG_QUEUE_CPU_MONDO_HEAD:
253 case MISCREG_QUEUE_CPU_MONDO_TAIL:
254 case MISCREG_QUEUE_DEV_MONDO_HEAD:
255 case MISCREG_QUEUE_DEV_MONDO_TAIL:
256 case MISCREG_QUEUE_RES_ERROR_HEAD:
257 case MISCREG_QUEUE_RES_ERROR_TAIL:
258 case MISCREG_QUEUE_NRES_ERROR_HEAD:
259 case MISCREG_QUEUE_NRES_ERROR_TAIL:
260 case MISCREG_SOFTINT:
261 case MISCREG_TICK_CMPR:
262 case MISCREG_STICK_CMPR:
263 case MISCREG_PIL:
264 case MISCREG_HPSTATE:
265 case MISCREG_HINTP:
266 case MISCREG_HTSTATE:
267 case MISCREG_HSTICK_CMPR:
268 return readMiscRegNoEffect(miscReg) ;
269
270 case MISCREG_HTBA:
271 return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF);
272 case MISCREG_HVER:
273 // XXX set to match Legion
274 return ULL(0x3e) << 48 |
275 ULL(0x23) << 32 |
276 ULL(0x20) << 24 |
277 // MaxGL << 16 | XXX For some reason legion doesn't set GL
278 MaxTL << 8 |
279 (NWindows -1) << 0;
280
281 case MISCREG_STRAND_STS_REG:
282 System *sys;
283 int x;
284 sys = tc->getSystemPtr();
285
286 temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative);
287 // Check that the CPU array is fully populated
288 // (by calling getNumCPus())
289 assert(sys->numContexts() > tc->contextId());
290
291 temp |= tc->contextId() << STS::shft_id;
292
293 for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) {
294 switch (sys->threadContexts[x]->status()) {
295 case ThreadContext::Active:
296 temp |= STS::st_run << (STS::shft_fsm0 -
297 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
298 break;
299 case ThreadContext::Suspended:
300 // should this be idle?
301 temp |= STS::st_idle << (STS::shft_fsm0 -
302 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
303 break;
304 case ThreadContext::Halted:
305 temp |= STS::st_halt << (STS::shft_fsm0 -
306 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
307 break;
308 default:
309 panic("What state are we in?!\n");
310 } // switch
311 } // for
312
313 return temp;
314 default:
315 panic("Invalid read to FS misc register\n");
316 }
317}
318
319void
320ISA::processTickCompare(ThreadContext *tc)
321{
322 panic("tick compare not implemented\n");
323}
324
325void
326ISA::processSTickCompare(ThreadContext *tc)
327{
328 BaseCPU *cpu = tc->getCpuPtr();
329
330 // since our microcode instructions take two cycles we need to check if
331 // we're actually at the correct cycle or we need to wait a little while
332 // more
333 int delay;
334 delay = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
335 cpu->instCount();
336 assert(delay >= 0 && "stick compare missed interrupt cycle");
337
338 if (delay == 0 || tc->status() == ThreadContext::Suspended) {
339 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
340 (stick_cmpr & mask(63)));
341 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
342 setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
343 }
344 } else {
345 cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(delay)));
346 }
347}
348
349void
350ISA::processHSTickCompare(ThreadContext *tc)
351{
352 BaseCPU *cpu = tc->getCpuPtr();
353
354 // since our microcode instructions take two cycles we need to check if
355 // we're actually at the correct cycle or we need to wait a little while
356 // more
357 int delay;
358 if ( tc->status() == ThreadContext::Halted)
359 return;
360
361 delay = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
362 cpu->instCount();
363 assert(delay >= 0 && "hstick compare missed interrupt cycle");
364
365 if (delay == 0 || tc->status() == ThreadContext::Suspended) {
366 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
367 (stick_cmpr & mask(63)));
368 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
369 setMiscReg(MISCREG_HINTP, 1, tc);
370 }
371 // Need to do something to cause interrupt to happen here !!! @todo
372 } else {
373 cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(delay)));
374 }
375}
376