ua2005.cc (4207:3ebd72381185) | ua2005.cc (4216:c01745179a1f) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 181 unchanged lines hidden (view full) --- 190 setRegNoEffect(miscReg, val); 191 break; 192 193 case MISCREG_STRAND_STS_REG: 194 if (bits(val,2,2)) 195 panic("No support for setting spec_en bit\n"); 196 setRegNoEffect(miscReg, bits(val,0,0)); 197 if (!bits(val,0,0)) { | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 181 unchanged lines hidden (view full) --- 190 setRegNoEffect(miscReg, val); 191 break; 192 193 case MISCREG_STRAND_STS_REG: 194 if (bits(val,2,2)) 195 panic("No support for setting spec_en bit\n"); 196 setRegNoEffect(miscReg, bits(val,0,0)); 197 if (!bits(val,0,0)) { |
198 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); |
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198 // Time to go to sleep 199 tc->suspend(); 200 if (tc->getKernelStats()) 201 tc->getKernelStats()->quiesce(); 202 } 203 break; 204 205 default: --- 96 unchanged lines hidden (view full) --- 302 // since our microcode instructions take two cycles we need to check if 303 // we're actually at the correct cycle or we need to wait a little while 304 // more 305 int ticks; 306 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 307 tc->getCpuPtr()->instCount(); 308 assert(ticks >= 0 && "stick compare missed interrupt cycle"); 309 | 199 // Time to go to sleep 200 tc->suspend(); 201 if (tc->getKernelStats()) 202 tc->getKernelStats()->quiesce(); 203 } 204 break; 205 206 default: --- 96 unchanged lines hidden (view full) --- 303 // since our microcode instructions take two cycles we need to check if 304 // we're actually at the correct cycle or we need to wait a little while 305 // more 306 int ticks; 307 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 308 tc->getCpuPtr()->instCount(); 309 assert(ticks >= 0 && "stick compare missed interrupt cycle"); 310 |
310 if (ticks == 0) { | 311 if (ticks == 0 || tc->status() == ThreadContext::Suspended) { |
311 DPRINTF(Timer, "STick compare cycle reached at %#x\n", 312 (stick_cmpr & mask(63))); 313 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 314 setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 315 } 316 } else 317 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 318} 319 320void 321MiscRegFile::processHSTickCompare(ThreadContext *tc) 322{ 323 // since our microcode instructions take two cycles we need to check if 324 // we're actually at the correct cycle or we need to wait a little while 325 // more 326 int ticks; | 312 DPRINTF(Timer, "STick compare cycle reached at %#x\n", 313 (stick_cmpr & mask(63))); 314 if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 315 setReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 316 } 317 } else 318 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 319} 320 321void 322MiscRegFile::processHSTickCompare(ThreadContext *tc) 323{ 324 // since our microcode instructions take two cycles we need to check if 325 // we're actually at the correct cycle or we need to wait a little while 326 // more 327 int ticks; |
328 if ( tc->status() == ThreadContext::Halted || 329 tc->status() == ThreadContext::Unallocated) 330 return; 331 |
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327 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 328 tc->getCpuPtr()->instCount(); 329 assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 330 | 332 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 333 tc->getCpuPtr()->instCount(); 334 assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 335 |
331 if (ticks == 0) { | 336 if (ticks == 0 || tc->status() == ThreadContext::Suspended) { |
332 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 333 (stick_cmpr & mask(63))); 334 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 335 setReg(MISCREG_HINTP, 1, tc); 336 } 337 // Need to do something to cause interrupt to happen here !!! @todo 338 } else 339 hSTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 340} 341 | 337 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 338 (stick_cmpr & mask(63))); 339 if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 340 setReg(MISCREG_HINTP, 1, tc); 341 } 342 // Need to do something to cause interrupt to happen here !!! @todo 343 } else 344 hSTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 345} 346 |