ua2005.cc (3921:0aa584f53a9b) | ua2005.cc (3923:a8ce86366fd3) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 36 unchanged lines hidden (view full) --- 45 setReg(miscReg, val);; 46 if (val != 0x10000 && val != 0) 47 warn("Writing to softint not really supported, writing: %#x\n", val); 48 break; 49 50 case MISCREG_SOFTINT_CLR: 51 return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc); 52 case MISCREG_SOFTINT_SET: | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 36 unchanged lines hidden (view full) --- 45 setReg(miscReg, val);; 46 if (val != 0x10000 && val != 0) 47 warn("Writing to softint not really supported, writing: %#x\n", val); 48 break; 49 50 case MISCREG_SOFTINT_CLR: 51 return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc); 52 case MISCREG_SOFTINT_SET: |
53 tc->getCpuPtr()->checkInterrupts = true; | |
54 tc->getCpuPtr()->post_interrupt(soft_interrupt); 55 return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc); 56 57 case MISCREG_TICK_CMPR: 58 if (tickCompare == NULL) 59 tickCompare = new TickCompareEvent(this, tc); 60 setReg(miscReg, val); 61 if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) --- 13 unchanged lines hidden (view full) --- 75 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 76 tc->getCpuPtr()->instCount(); 77 if (!(stick_cmpr & ~mask(63)) && time > 0) 78 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick); 79 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 80 break; 81 82 case MISCREG_PSTATE: | 53 tc->getCpuPtr()->post_interrupt(soft_interrupt); 54 return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc); 55 56 case MISCREG_TICK_CMPR: 57 if (tickCompare == NULL) 58 tickCompare = new TickCompareEvent(this, tc); 59 setReg(miscReg, val); 60 if ((tick_cmpr & mask(63)) && tickCompare->scheduled()) --- 13 unchanged lines hidden (view full) --- 74 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 75 tc->getCpuPtr()->instCount(); 76 if (!(stick_cmpr & ~mask(63)) && time > 0) 77 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick); 78 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 79 break; 80 81 case MISCREG_PSTATE: |
83 if (val & PSTATE::ie && !(pstate & PSTATE::ie)) { 84 tc->getCpuPtr()->checkInterrupts = true; 85 } | |
86 setReg(miscReg, val); 87 88 case MISCREG_PIL: | 82 setReg(miscReg, val); 83 84 case MISCREG_PIL: |
89 if (val < pil) { 90 tc->getCpuPtr()->checkInterrupts = true; 91 } | |
92 setReg(miscReg, val); 93 break; 94 95 case MISCREG_HVER: 96 panic("Shouldn't be writing HVER\n"); 97 98 case MISCREG_HINTP: 99 setReg(miscReg, val); --- 7 unchanged lines hidden (view full) --- 107 case MISCREG_QUEUE_CPU_MONDO_TAIL: 108 case MISCREG_QUEUE_DEV_MONDO_HEAD: 109 case MISCREG_QUEUE_DEV_MONDO_TAIL: 110 case MISCREG_QUEUE_RES_ERROR_HEAD: 111 case MISCREG_QUEUE_RES_ERROR_TAIL: 112 case MISCREG_QUEUE_NRES_ERROR_HEAD: 113 case MISCREG_QUEUE_NRES_ERROR_TAIL: 114 setReg(miscReg, val); | 85 setReg(miscReg, val); 86 break; 87 88 case MISCREG_HVER: 89 panic("Shouldn't be writing HVER\n"); 90 91 case MISCREG_HINTP: 92 setReg(miscReg, val); --- 7 unchanged lines hidden (view full) --- 100 case MISCREG_QUEUE_CPU_MONDO_TAIL: 101 case MISCREG_QUEUE_DEV_MONDO_HEAD: 102 case MISCREG_QUEUE_DEV_MONDO_TAIL: 103 case MISCREG_QUEUE_RES_ERROR_HEAD: 104 case MISCREG_QUEUE_RES_ERROR_TAIL: 105 case MISCREG_QUEUE_NRES_ERROR_HEAD: 106 case MISCREG_QUEUE_NRES_ERROR_TAIL: 107 setReg(miscReg, val); |
115 tc->getCpuPtr()->checkInterrupts = true; | 108 //do something to post mondo interrupt |
116 break; 117 118 case MISCREG_HSTICK_CMPR: 119 if (hSTickCompare == NULL) 120 hSTickCompare = new HSTickCompareEvent(this, tc); 121 setReg(miscReg, val); 122 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 123 hSTickCompare->deschedule(); --- 79 unchanged lines hidden (view full) --- 203 tc->getCpuPtr()->instCount(); 204 assert(ticks >= 0 && "stick compare missed interrupt cycle"); 205 206 if (ticks == 0) { 207 DPRINTF(Timer, "STick compare cycle reached at %#x\n", 208 (stick_cmpr & mask(63))); 209 if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 210 tc->getCpuPtr()->post_interrupt(soft_interrupt); | 109 break; 110 111 case MISCREG_HSTICK_CMPR: 112 if (hSTickCompare == NULL) 113 hSTickCompare = new HSTickCompareEvent(this, tc); 114 setReg(miscReg, val); 115 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 116 hSTickCompare->deschedule(); --- 79 unchanged lines hidden (view full) --- 196 tc->getCpuPtr()->instCount(); 197 assert(ticks >= 0 && "stick compare missed interrupt cycle"); 198 199 if (ticks == 0) { 200 DPRINTF(Timer, "STick compare cycle reached at %#x\n", 201 (stick_cmpr & mask(63))); 202 if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 203 tc->getCpuPtr()->post_interrupt(soft_interrupt); |
211 tc->getCpuPtr()->checkInterrupts = true; | |
212 setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 213 } 214 } else 215 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 216} 217 218void 219MiscRegFile::processHSTickCompare(ThreadContext *tc) --- 7 unchanged lines hidden (view full) --- 227 assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 228 229 if (ticks == 0) { 230 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 231 (stick_cmpr & mask(63))); 232 if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 233 setRegWithEffect(MISCREG_HINTP, 1, tc); 234 tc->getCpuPtr()->post_interrupt(hstick_match); | 204 setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 205 } 206 } else 207 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 208} 209 210void 211MiscRegFile::processHSTickCompare(ThreadContext *tc) --- 7 unchanged lines hidden (view full) --- 219 assert(ticks >= 0 && "hstick compare missed interrupt cycle"); 220 221 if (ticks == 0) { 222 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 223 (stick_cmpr & mask(63))); 224 if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 225 setRegWithEffect(MISCREG_HINTP, 1, tc); 226 tc->getCpuPtr()->post_interrupt(hstick_match); |
235 tc->getCpuPtr()->checkInterrupts = true; | |
236 } 237 // Need to do something to cause interrupt to happen here !!! @todo 238 } else 239 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 240} 241 | 227 } 228 // Need to do something to cause interrupt to happen here !!! @todo 229 } else 230 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick); 231} 232 |