ua2005.cc (2680:246e7104f744) | ua2005.cc (2982:0ecdb0879b14) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32 33Fault 34SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 35 ThreadContext *tc) 36{ 37 int64_t time; 38 SparcSystem *sys; 39 switch (miscReg) { | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32 33Fault 34SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 35 ThreadContext *tc) 36{ 37 int64_t time; 38 SparcSystem *sys; 39 switch (miscReg) { |
40 /** Full system only ASRs */ | 40 /* Full system only ASRs */ |
41 case MISCREG_SOFTINT: 42 if (isNonPriv()) 43 return new PrivilegedOpcode; 44 // Check if we are going to interrupt because of something 45 int oldLevel = InterruptLevel(softint); 46 int newLevel = InterruptLevel(val); 47 setReg(miscReg, val); 48 if (newLevel > oldLevel) --- 40 unchanged lines hidden (view full) --- 89 setReg(miscReg, val); 90 if (stick_cmprFields.int_dis && sTickCompare.scheduled()) 91 sTickCompare.deschedule(); 92 time = stick_cmprFields.tick_cmpr - sys->sysTick; 93 if (!stick_cmprFields.int_dis && time > 0) 94 sTickCompare.schedule(time * Clock::Int::ns); 95 return NoFault; 96 | 41 case MISCREG_SOFTINT: 42 if (isNonPriv()) 43 return new PrivilegedOpcode; 44 // Check if we are going to interrupt because of something 45 int oldLevel = InterruptLevel(softint); 46 int newLevel = InterruptLevel(val); 47 setReg(miscReg, val); 48 if (newLevel > oldLevel) --- 40 unchanged lines hidden (view full) --- 89 setReg(miscReg, val); 90 if (stick_cmprFields.int_dis && sTickCompare.scheduled()) 91 sTickCompare.deschedule(); 92 time = stick_cmprFields.tick_cmpr - sys->sysTick; 93 if (!stick_cmprFields.int_dis && time > 0) 94 sTickCompare.schedule(time * Clock::Int::ns); 95 return NoFault; 96 |
97 /** Fullsystem only Priv registers. */ | 97 /* Fullsystem only Priv registers. */ |
98 case MISCREG_PIL: 99 if (FULL_SYSTEM) { 100 setReg(miscReg, val); 101 //tc->getCpuPtr()->checkInterrupts; 102 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 103 return NoFault; 104 } else 105 panic("PIL not implemented for syscall emulation\n"); 106 | 98 case MISCREG_PIL: 99 if (FULL_SYSTEM) { 100 setReg(miscReg, val); 101 //tc->getCpuPtr()->checkInterrupts; 102 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 103 return NoFault; 104 } else 105 panic("PIL not implemented for syscall emulation\n"); 106 |
107 /** Hyper privileged registers */ | 107 /* Hyper privileged registers */ |
108 case MISCREG_HPSTATE: 109 case MISCREG_HINTP: 110 setReg(miscReg, val); 111 return NoFault; 112 case MISCREG_HTSTATE: 113 if (tl == 0) 114 return new IllegalInstruction; 115 setReg(miscReg, val); --- 26 unchanged lines hidden (view full) --- 142 } 143} 144 145MiscReg 146MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc) 147{ 148 switch (miscReg) { 149 | 108 case MISCREG_HPSTATE: 109 case MISCREG_HINTP: 110 setReg(miscReg, val); 111 return NoFault; 112 case MISCREG_HTSTATE: 113 if (tl == 0) 114 return new IllegalInstruction; 115 setReg(miscReg, val); --- 26 unchanged lines hidden (view full) --- 142 } 143} 144 145MiscReg 146MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc) 147{ 148 switch (miscReg) { 149 |
150 /** Privileged registers. */ | 150 /* Privileged registers. */ |
151 case MISCREG_SOFTINT: 152 if (isNonPriv()) { 153 fault = new PrivilegedOpcode; 154 return 0; 155 } 156 return readReg(miscReg); 157 case MISCREG_TICK_CMPR: 158 if (isNonPriv()) { --- 13 unchanged lines hidden (view full) --- 172 case MISCREG_STICK_CMPR: 173 if (isNonPriv()) { 174 fault = new PrivilegedOpcode; 175 return 0; 176 } 177 return readReg(miscReg); 178 179 | 151 case MISCREG_SOFTINT: 152 if (isNonPriv()) { 153 fault = new PrivilegedOpcode; 154 return 0; 155 } 156 return readReg(miscReg); 157 case MISCREG_TICK_CMPR: 158 if (isNonPriv()) { --- 13 unchanged lines hidden (view full) --- 172 case MISCREG_STICK_CMPR: 173 if (isNonPriv()) { 174 fault = new PrivilegedOpcode; 175 return 0; 176 } 177 return readReg(miscReg); 178 179 |
180 /** Hyper privileged registers */ | 180 /* Hyper privileged registers */ |
181 case MISCREG_HPSTATE: 182 case MISCREG_HINTP: 183 return readReg(miscReg); 184 case MISCREG_HTSTATE: 185 if (tl == 0) { 186 fault = new IllegalInstruction; 187 return 0; 188 } --- 36 unchanged lines hidden --- | 181 case MISCREG_HPSTATE: 182 case MISCREG_HINTP: 183 return readReg(miscReg); 184 case MISCREG_HTSTATE: 185 if (tl == 0) { 186 fault = new IllegalInstruction; 187 return 0; 188 } --- 36 unchanged lines hidden --- |