ua2005.cc (11793:ef606668d247) | ua2005.cc (12620:fe5cdc0293dd) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 123 unchanged lines hidden (view full) --- 132 cpu->deschedule(sTickCompare); 133 cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(time))); 134 } 135 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 136 break; 137 138 case MISCREG_PSTATE: 139 setMiscRegNoEffect(miscReg, val); | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 123 unchanged lines hidden (view full) --- 132 cpu->deschedule(sTickCompare); 133 cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(time))); 134 } 135 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 136 break; 137 138 case MISCREG_PSTATE: 139 setMiscRegNoEffect(miscReg, val); |
140 break; |
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140 141 case MISCREG_PIL: 142 setMiscRegNoEffect(miscReg, val); 143 checkSoftInt(tc); 144 break; 145 146 case MISCREG_HVER: 147 panic("Shouldn't be writing HVER\n"); --- 228 unchanged lines hidden --- | 141 142 case MISCREG_PIL: 143 setMiscRegNoEffect(miscReg, val); 144 checkSoftInt(tc); 145 break; 146 147 case MISCREG_HVER: 148 panic("Shouldn't be writing HVER\n"); --- 228 unchanged lines hidden --- |