1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "arch/sparc/regfile.hh"
30
31Fault
32SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
33 ExecContext *xc)
34{
35 int64_t time;
36 SparcSystem *sys;
37 switch (miscReg) {
38 /** Full system only ASRs */
39 case MISCREG_SOFTINT:
40 if (isNonPriv())
41 return new PrivilegedOpcode;
42 // Check if we are going to interrupt because of something
43 int oldLevel = InterruptLevel(softint);
44 int newLevel = InterruptLevel(val);
45 setReg(miscReg, val);
46 if (newLevel > oldLevel)
47 ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
48 //xc->getCpuPtr()->checkInterrupts = true;
49 return NoFault;
50
51 case MISCREG_SOFTINT_CLR:
52 return setRegWithEffect(miscReg, ~val & softint, xc);
53 case MISCREG_SOFTINT_SET:
54 return setRegWithEffect(miscReg, val | softint, xc);
55
56 case MISCREG_TICK_CMPR:
57 if (isNonPriv())
58 return new PrivilegedOpcode;
59 if (tickCompare == NULL)
60 tickCompare = new TickCompareEvent(this, xc);
61 setReg(miscReg, val);
62 if (tick_cmprFields.int_dis && tickCompare.scheduled())
63 tickCompare.deschedule();
64 time = tick_cmprFields.tick_cmpr - tickFields.counter;
65 if (!tick_cmprFields.int_dis && time > 0)
66 tickCompare.schedule(time * xc->getCpuPtr()->cycles(1));
67 return NoFault;
68
69 case MISCREG_STICK:
70 if (isNonPriv())
71 return new PrivilegedOpcode;
72 if (isPriv())
73 return new PrivilegedAction;
74 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
75 assert(sys != NULL);
76 sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
77 stickFields.npt = val & Bit64 ? 1 : 0;
78 return NoFault;
79
80 case MISCREG_STICK_CMPR:
81 if (isNonPriv())
82 return new PrivilegedOpcode;
83 if (sTickCompare == NULL)
84 sTickCompare = new STickCompareEvent(this, xc);
85 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
86 assert(sys != NULL);
87 setReg(miscReg, val);
88 if (stick_cmprFields.int_dis && sTickCompare.scheduled())
89 sTickCompare.deschedule();
90 time = stick_cmprFields.tick_cmpr - sys->sysTick;
91 if (!stick_cmprFields.int_dis && time > 0)
92 sTickCompare.schedule(time * Clock::Int::ns);
93 return NoFault;
94
95 /** Fullsystem only Priv registers. */
96 case MISCREG_PIL:
97 if (FULL_SYSTEM) {
98 setReg(miscReg, val);
99 //xc->getCpuPtr()->checkInterrupts;
100 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
101 return NoFault;
102 } else
103 panic("PIL not implemented for syscall emulation\n");
104
105 /** Hyper privileged registers */
106 case MISCREG_HPSTATE:
107 case MISCREG_HINTP:
108 setReg(miscReg, val);
109 return NoFault;
110 case MISCREG_HTSTATE:
111 if (tl == 0)
112 return new IllegalInstruction;
113 setReg(miscReg, val);
114 return NoFault;
115
116 case MISCREG_HTBA:
117 // clear lower 7 bits on writes.
118 setReg(miscReg, val & ULL(~0x7FFF));
119 return NoFault;
120
121 case MISCREG_STRAND_STS_REG:
122 setReg(miscReg, strandStatusReg);
123 return NoFault;
124 case MISCREG_HSTICK_CMPR:
125 if (isNonPriv())
126 return new PrivilegedOpcode;
127 if (hSTickCompare == NULL)
128 hSTickCompare = new HSTickCompareEvent(this, xc);
129 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
130 assert(sys != NULL);
131 setReg(miscReg, val);
132 if (hstick_cmprFields.int_dis && hSTickCompare.scheduled())
133 hSTickCompare.deschedule();
134 int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick;
135 if (!hstick_cmprFields.int_dis && time > 0)
136 hSTickCompare.schedule(time * Clock::Int::ns);
137 return NoFault;
138 default:
139 return new IllegalInstruction;
140 }
141}
142
143MiscReg
144MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc)
145{
146 switch (miscReg) {
147
148 /** Privileged registers. */
149 case MISCREG_SOFTINT:
150 if (isNonPriv()) {
151 fault = new PrivilegedOpcode;
152 return 0;
153 }
154 return readReg(miscReg);
155 case MISCREG_TICK_CMPR:
156 if (isNonPriv()) {
157 fault = new PrivilegedOpcode;
158 return 0;
159 }
160 return readReg(miscReg);
161 case MISCREG_STICK:
162 SparcSystem *sys;
163 if (stickFields.npt && !isNonPriv()) {
164 fault = new PrivilegedAction;
165 return 0;
166 }
167 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
168 assert(sys != NULL);
169 return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
170 case MISCREG_STICK_CMPR:
171 if (isNonPriv()) {
172 fault = new PrivilegedOpcode;
173 return 0;
174 }
175 return readReg(miscReg);
176
177
178 /** Hyper privileged registers */
179 case MISCREG_HPSTATE:
180 case MISCREG_HINTP:
181 return readReg(miscReg);
182 case MISCREG_HTSTATE:
183 if (tl == 0) {
184 fault = new IllegalInstruction;
185 return 0;
186 }
187 return readReg(miscReg);
188
189 case MISCREG_HTBA:
190 return readReg(miscReg) & ULL(~0x7FFF);
191 case MISCREG_HVER:
192 return NWindows | MaxTL << 8 | MaxGL << 16;
193 case MISCREG_STRAND_STS_REG:
194 return strandStatusReg;
195 case MISCREG_HSTICK_CMPR:
196 return hstick_cmpr;
197
198 default:
199 fault = new IllegalInstruction;
200 return 0;
201 }
202}
203
204void
205MiscRegFile::processTickCompare(ExecContext *xc)
206{
207 panic("tick compare not implemented\n");
208}
209
210void
211MiscRegFile::processSTickCompare(ExecContext *xc)
212{
213 panic("tick compare not implemented\n");
214}
215
216void
217MiscRegFile::processHSTickCompare(ExecContext *xc)
218{
219 panic("tick compare not implemented\n");
220}
221
222}; // namespace SparcISA