1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31#include "arch/sparc/registers.hh"
32#include "base/bitfield.hh"
33#include "base/trace.hh"
34#include "cpu/base.hh"
35#include "cpu/thread_context.hh"
36#include "debug/Quiesce.hh"
37#include "debug/Timer.hh"
38#include "sim/system.hh"
39
40using namespace SparcISA;
41using namespace std;
42
43
44void
45ISA::checkSoftInt(ThreadContext *tc)
46{

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219 case MISCREG_STRAND_STS_REG:
220 if (bits(val,2,2))
221 panic("No support for setting spec_en bit\n");
222 setMiscRegNoEffect(miscReg, bits(val,0,0));
223 if (!bits(val,0,0)) {
224 DPRINTF(Quiesce, "Cpu executed quiescing instruction\n");
225 // Time to go to sleep
226 tc->suspend();
227#if FULL_SYSTEM
228 if (tc->getKernelStats())
229 tc->getKernelStats()->quiesce();
230#endif
231 }
232 break;
233
234 default:
235 panic("Invalid write to FS misc register %s\n",
236 getMiscRegName(miscReg));
237 }
238}

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