1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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45 setReg(miscReg, val);;
46 if (val != 0x10000 && val != 0)
47 warn("Writing to softint not really supported, writing: %#x\n", val);
48 break;
49
50 case MISCREG_SOFTINT_CLR:
51 return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
52 case MISCREG_SOFTINT_SET:
53 tc->getCpuPtr()->checkInterrupts = true;
54 tc->getCpuPtr()->post_interrupt(soft_interrupt);
55 return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
56
57 case MISCREG_TICK_CMPR:
58 if (tickCompare == NULL)
59 tickCompare = new TickCompareEvent(this, tc);
60 setReg(miscReg, val);
61 if ((tick_cmpr & mask(63)) && tickCompare->scheduled())

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75 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
76 tc->getCpuPtr()->instCount();
77 if (!(stick_cmpr & ~mask(63)) && time > 0)
78 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
79 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
80 break;
81
82 case MISCREG_PSTATE:
83 if (val & PSTATE::ie && !(pstate & PSTATE::ie)) {
84 tc->getCpuPtr()->checkInterrupts = true;
85 }
86 setReg(miscReg, val);
87
88 case MISCREG_PIL:
89 if (val < pil) {
90 tc->getCpuPtr()->checkInterrupts = true;
91 }
92 setReg(miscReg, val);
93 break;
94
95 case MISCREG_HVER:
96 panic("Shouldn't be writing HVER\n");
97
98 case MISCREG_HINTP:
99 setReg(miscReg, val);

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107 case MISCREG_QUEUE_CPU_MONDO_TAIL:
108 case MISCREG_QUEUE_DEV_MONDO_HEAD:
109 case MISCREG_QUEUE_DEV_MONDO_TAIL:
110 case MISCREG_QUEUE_RES_ERROR_HEAD:
111 case MISCREG_QUEUE_RES_ERROR_TAIL:
112 case MISCREG_QUEUE_NRES_ERROR_HEAD:
113 case MISCREG_QUEUE_NRES_ERROR_TAIL:
114 setReg(miscReg, val);
115 tc->getCpuPtr()->checkInterrupts = true;
116 break;
117
118 case MISCREG_HSTICK_CMPR:
119 if (hSTickCompare == NULL)
120 hSTickCompare = new HSTickCompareEvent(this, tc);
121 setReg(miscReg, val);
122 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
123 hSTickCompare->deschedule();

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203 tc->getCpuPtr()->instCount();
204 assert(ticks >= 0 && "stick compare missed interrupt cycle");
205
206 if (ticks == 0) {
207 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
208 (stick_cmpr & mask(63)));
209 if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
210 tc->getCpuPtr()->post_interrupt(soft_interrupt);
211 tc->getCpuPtr()->checkInterrupts = true;
212 setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
213 }
214 } else
215 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
216}
217
218void
219MiscRegFile::processHSTickCompare(ThreadContext *tc)

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227 assert(ticks >= 0 && "hstick compare missed interrupt cycle");
228
229 if (ticks == 0) {
230 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
231 (stick_cmpr & mask(63)));
232 if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
233 setRegWithEffect(MISCREG_HINTP, 1, tc);
234 tc->getCpuPtr()->post_interrupt(hstick_match);
235 tc->getCpuPtr()->checkInterrupts = true;
236 }
237 // Need to do something to cause interrupt to happen here !!! @todo
238 } else
239 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
240}
241