1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 28 unchanged lines hidden (view full) ---

37void
38MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
39 ThreadContext *tc)
40{
41 int64_t time;
42 switch (miscReg) {
43 /* Full system only ASRs */
44 case MISCREG_SOFTINT:
45 // Check if we are going to interrupt because of something
46 setReg(miscReg, val);
47 tc->getCpuPtr()->checkInterrupts = true;
48 tc->getCpuPtr()->post_interrupt(hstick_match);
49 if (val != 0x10000 && val != 0)
50 warn("Writing to softint not really supported, writing: %#x\n", val);
51 break;
52
53 case MISCREG_SOFTINT_CLR:
54 return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
55 case MISCREG_SOFTINT_SET:
56 return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
57
58 case MISCREG_TICK_CMPR:
59 if (tickCompare == NULL)
60 tickCompare = new TickCompareEvent(this, tc);
61 setReg(miscReg, val);
62 if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
63 tickCompare->deschedule();

--- 27 unchanged lines hidden (view full) ---

91 tc->getCpuPtr()->checkInterrupts = true;
92 }
93 setReg(miscReg, val);
94 break;
95
96 case MISCREG_HVER:
97 panic("Shouldn't be writing HVER\n");
98
99 case MISCREG_HTBA:
100 // clear lower 7 bits on writes.
101 setReg(miscReg, val & ULL(~0x7FFF));
102 break;
103
104 case MISCREG_QUEUE_CPU_MONDO_HEAD:
105 case MISCREG_QUEUE_CPU_MONDO_TAIL:
106 case MISCREG_QUEUE_DEV_MONDO_HEAD:

--- 92 unchanged lines hidden (view full) ---

199 int ticks;
200 ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
201 tc->getCpuPtr()->instCount();
202 assert(ticks >= 0 && "stick compare missed interrupt cycle");
203
204 if (ticks == 0) {
205 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
206 (stick_cmpr & mask(63)));
207 tc->getCpuPtr()->post_interrupt(soft_interrupt);
208 tc->getCpuPtr()->checkInterrupts = true;
209 softint |= ULL(1) << 16;
210 } else
211 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
212}
213
214void
215MiscRegFile::processHSTickCompare(ThreadContext *tc)
216{
217 // since our microcode instructions take two cycles we need to check if
218 // we're actually at the correct cycle or we need to wait a little while
219 // more
220 int ticks;
221 ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
222 tc->getCpuPtr()->instCount();
223 assert(ticks >= 0 && "hstick compare missed interrupt cycle");
224
225 if (ticks == 0) {
226 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
227 (stick_cmpr & mask(63)));
228 tc->getCpuPtr()->post_interrupt(hstick_match);
229 tc->getCpuPtr()->checkInterrupts = true;
230 // Need to do something to cause interrupt to happen here !!! @todo
231 } else
232 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
233}
234