1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38
39void
40MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
41 ThreadContext *tc)
42{
43 int64_t time;
44 int oldLevel, newLevel;
45 switch (miscReg) {
46 /* Full system only ASRs */
47 case MISCREG_SOFTINT:
48 // Check if we are going to interrupt because of something
49 oldLevel = InterruptLevel(softint);
50 newLevel = InterruptLevel(val);
51 setReg(miscReg, val);
52 if (newLevel > oldLevel)
53 ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
54 //tc->getCpuPtr()->checkInterrupts = true;
55 panic("SOFTINT not implemented\n");
56 break;
57
58 case MISCREG_SOFTINT_CLR:
59 return setRegWithEffect(miscReg, ~val & softint, tc);
60 case MISCREG_SOFTINT_SET:
61 return setRegWithEffect(miscReg, val | softint, tc);
62
63 case MISCREG_TICK_CMPR:
64 if (tickCompare == NULL)
65 tickCompare = new TickCompareEvent(this, tc);
66 setReg(miscReg, val);
67 if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
68 tickCompare->deschedule();
69 time = (tick_cmpr & mask(63)) - (tick & mask(63));
70 if (!(tick_cmpr & ~mask(63)) && time > 0)
71 tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
72 break;
73
74 case MISCREG_STICK_CMPR:
75 if (sTickCompare == NULL)
76 sTickCompare = new STickCompareEvent(this, tc);
77 setReg(miscReg, val);
78 if ((stick_cmpr & mask(63)) && sTickCompare->scheduled())
79 sTickCompare->deschedule();
80 time = (stick_cmpr & mask(63)) - (stick & mask(63));
81 if (!(stick_cmpr & ~mask(63)) && time > 0)
82 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
83 break;
84
85 case MISCREG_PIL:
86 setReg(miscReg, val);
87 //tc->getCpuPtr()->checkInterrupts;
88 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
89 panic("PIL not implemented\n");
90 break;
91
92 case MISCREG_HVER:
93 panic("Shouldn't be writing HVER\n");
94
95 case MISCREG_HTBA:
96 // clear lower 7 bits on writes.
97 setReg(miscReg, val & ULL(~0x7FFF));
98 break;
99
100 case MISCREG_HSTICK_CMPR:
101 if (hSTickCompare == NULL)
102 hSTickCompare = new HSTickCompareEvent(this, tc);
103 setReg(miscReg, val);
104 if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled())
105 hSTickCompare->deschedule();
106 time = (hstick_cmpr & mask(63)) - (stick & mask(63));
107 if (!(hstick_cmpr & ~mask(63)) && time > 0)
108 hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
109 break;
110
111 case MISCREG_HPSTATE:
112 case MISCREG_HTSTATE:
113 case MISCREG_STRAND_STS_REG:
114 setReg(miscReg, val);
115 break;
116
117 default:
118 panic("Invalid write to FS misc register\n");
119 }
120}
121
122MiscReg
123MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
124{
125 switch (miscReg) {
126
127 /* Privileged registers. */
128 case MISCREG_SOFTINT:
129 case MISCREG_TICK_CMPR:
130 case MISCREG_STICK_CMPR:
131 case MISCREG_PIL:
132 case MISCREG_HPSTATE:
133 case MISCREG_HINTP:
134 case MISCREG_HTSTATE:
135 case MISCREG_STRAND_STS_REG:
136 case MISCREG_HSTICK_CMPR:
137 return readReg(miscReg) ;
138
139 case MISCREG_HTBA:
140 return readReg(miscReg) & ULL(~0x7FFF);
141 case MISCREG_HVER:
142 return NWindows | MaxTL << 8 | MaxGL << 16;
143
144 default:
145 panic("Invalid read to FS misc register\n");
146 }
147}
148/*
149 In Niagra STICK==TICK so this isn't needed
150 case MISCREG_STICK:
151 SparcSystem *sys;
152 sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
153 assert(sys != NULL);

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