1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
39 ThreadContext *tc)
40{
41 int64_t time;
42 switch (miscReg) {
43 /* Full system only ASRs */
44 case MISCREG_SOFTINT:
45 setReg(miscReg, val);;
46 break;
47
48 case MISCREG_SOFTINT_CLR:
49 return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
50 case MISCREG_SOFTINT_SET:
51 tc->getCpuPtr()->checkInterrupts = true;
52 tc->getCpuPtr()->post_interrupt(soft_interrupt);
53 return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
54
55 case MISCREG_TICK_CMPR:
56 if (tickCompare == NULL)
57 tickCompare = new TickCompareEvent(this, tc);
58 setReg(miscReg, val);
59 if ((tick_cmpr & mask(63)) && tickCompare->scheduled())

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73 time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
74 tc->getCpuPtr()->instCount();
75 if (!(stick_cmpr & ~mask(63)) && time > 0)
76 sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
77 DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
78 break;
79
80 case MISCREG_PSTATE:
81 if (val & PSTATE::ie && !(pstate & PSTATE::ie)) {
82 tc->getCpuPtr()->checkInterrupts = true;
83 }
84 setReg(miscReg, val);
85
86 case MISCREG_PIL:
87 if (val < pil) {
88 tc->getCpuPtr()->checkInterrupts = true;
89 }
90 setReg(miscReg, val);
91 break;
92
93 case MISCREG_HVER:
94 panic("Shouldn't be writing HVER\n");
95
96 case MISCREG_HINTP:
97 setReg(miscReg, val);

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105 case MISCREG_QUEUE_CPU_MONDO_TAIL:
106 case MISCREG_QUEUE_DEV_MONDO_HEAD:
107 case MISCREG_QUEUE_DEV_MONDO_TAIL:
108 case MISCREG_QUEUE_RES_ERROR_HEAD:
109 case MISCREG_QUEUE_RES_ERROR_TAIL:
110 case MISCREG_QUEUE_NRES_ERROR_HEAD:
111 case MISCREG_QUEUE_NRES_ERROR_TAIL:
112 setReg(miscReg, val);
113 tc->getCpuPtr()->checkInterrupts = true;
114 break;
115
116 case MISCREG_HSTICK_CMPR:
117 if (hSTickCompare == NULL)
118 hSTickCompare = new HSTickCompareEvent(this, tc);
119 setReg(miscReg, val);
120 if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
121 hSTickCompare->deschedule();

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201 tc->getCpuPtr()->instCount();
202 assert(ticks >= 0 && "stick compare missed interrupt cycle");
203
204 if (ticks == 0) {
205 DPRINTF(Timer, "STick compare cycle reached at %#x\n",
206 (stick_cmpr & mask(63)));
207 if (!(tc->readMiscReg(MISCREG_STICK_CMPR) & (ULL(1) << 63))) {
208 tc->getCpuPtr()->post_interrupt(soft_interrupt);
209 tc->getCpuPtr()->checkInterrupts = true;
210 setRegWithEffect(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc);
211 }
212 } else
213 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
214}
215
216void
217MiscRegFile::processHSTickCompare(ThreadContext *tc)

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225 assert(ticks >= 0 && "hstick compare missed interrupt cycle");
226
227 if (ticks == 0) {
228 DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
229 (stick_cmpr & mask(63)));
230 if (!(tc->readMiscReg(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) {
231 setRegWithEffect(MISCREG_HINTP, 1, tc);
232 tc->getCpuPtr()->post_interrupt(hstick_match);
233 tc->getCpuPtr()->checkInterrupts = true;
234 }
235 // Need to do something to cause interrupt to happen here !!! @todo
236 } else
237 sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
238}
239