types.hh (7720:65d338a8dba4) types.hh (7741:340b6f01d69b)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32#define __ARCH_SPARC_TYPES_HH__
33
34#include "base/bigint.hh"
35#include "base/types.hh"
36#include "arch/generic/types.hh"
37
38namespace SparcISA
39{
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 23 unchanged lines hidden (view full) ---

32#define __ARCH_SPARC_TYPES_HH__
33
34#include "base/bigint.hh"
35#include "base/types.hh"
36#include "arch/generic/types.hh"
37
38namespace SparcISA
39{
40 typedef uint32_t MachInst;
41 typedef uint64_t ExtMachInst;
42
40
43 typedef GenericISA::DelaySlotUPCState<MachInst> PCState;
41typedef uint32_t MachInst;
42typedef uint64_t ExtMachInst;
44
43
45 typedef Twin64_t LargestRead;
44typedef GenericISA::DelaySlotUPCState<MachInst> PCState;
46
45
47 struct CoreSpecific {
48 int core_type;
49 };
46typedef Twin64_t LargestRead;
47
48struct CoreSpecific
49{
50 int core_type;
51};
52
50}
51
52#endif
53}
54
55#endif