types.hh (11300:b3f2de9ff2bd) | types.hh (12386:2bf5fb25a5f1) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_SPARC_TYPES_HH__ 32#define __ARCH_SPARC_TYPES_HH__ 33 34#include "arch/generic/types.hh" | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 * 28 * Authors: Gabe Black 29 */ 30 31#ifndef __ARCH_SPARC_TYPES_HH__ 32#define __ARCH_SPARC_TYPES_HH__ 33 34#include "arch/generic/types.hh" |
35#include "base/bigint.hh" | |
36#include "base/types.hh" 37 38namespace SparcISA 39{ 40 41typedef uint32_t MachInst; 42typedef uint64_t ExtMachInst; 43 44typedef GenericISA::DelaySlotUPCState<MachInst> PCState; 45 46} 47 48#endif | 35#include "base/types.hh" 36 37namespace SparcISA 38{ 39 40typedef uint32_t MachInst; 41typedef uint64_t ExtMachInst; 42 43typedef GenericISA::DelaySlotUPCState<MachInst> PCState; 44 45} 46 47#endif |