tlb.hh (5894:8091ac99341a) tlb.hh (6022:410194bb3049)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
37#include "config/full_system.hh"
38#include "mem/request.hh"
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
37#include "config/full_system.hh"
38#include "mem/request.hh"
39#include "params/SparcDTB.hh"
40#include "params/SparcITB.hh"
39#include "params/SparcTLB.hh"
41#include "sim/faults.hh"
42#include "sim/tlb.hh"
43
44class ThreadContext;
45class Packet;
46
47namespace SparcISA
48{
49
50class TLB : public BaseTLB
51{
52#if !FULL_SYSTEM
53 //These faults need to be able to populate the tlb in SE mode.
54 friend class FastInstructionAccessMMUMiss;
55 friend class FastDataAccessMMUMiss;
56#endif
57
58 //TLB state
59 protected:
40#include "sim/faults.hh"
41#include "sim/tlb.hh"
42
43class ThreadContext;
44class Packet;
45
46namespace SparcISA
47{
48
49class TLB : public BaseTLB
50{
51#if !FULL_SYSTEM
52 //These faults need to be able to populate the tlb in SE mode.
53 friend class FastInstructionAccessMMUMiss;
54 friend class FastDataAccessMMUMiss;
55#endif
56
57 //TLB state
58 protected:
59 // Only used when this is the data TLB.
60 uint64_t sfar;
60 uint64_t c0_tsb_ps0;
61 uint64_t c0_tsb_ps1;
62 uint64_t c0_config;
63 uint64_t cx_tsb_ps0;
64 uint64_t cx_tsb_ps1;
65 uint64_t cx_config;
66 uint64_t sfsr;
67 uint64_t tag_access;

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143 void writeSfsr(bool write, ContextType ct,
144 bool se, FaultTypes ft, int asi);
145
146 void clearUsedBits();
147
148
149 void writeTagAccess(Addr va, int context);
150
61 uint64_t c0_tsb_ps0;
62 uint64_t c0_tsb_ps1;
63 uint64_t c0_config;
64 uint64_t cx_tsb_ps0;
65 uint64_t cx_tsb_ps1;
66 uint64_t cx_config;
67 uint64_t sfsr;
68 uint64_t tag_access;

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144 void writeSfsr(bool write, ContextType ct,
145 bool se, FaultTypes ft, int asi);
146
147 void clearUsedBits();
148
149
150 void writeTagAccess(Addr va, int context);
151
152 Fault translateInst(RequestPtr req, ThreadContext *tc);
153 Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
154
151 public:
152 typedef SparcTLBParams Params;
153 TLB(const Params *p);
154
155 void demapPage(Addr vaddr, uint64_t asn)
156 {
157 panic("demapPage(Addr) is not implemented.\n");
158 }
159
160 void dumpAll();
161
155 public:
156 typedef SparcTLBParams Params;
157 TLB(const Params *p);
158
159 void demapPage(Addr vaddr, uint64_t asn)
160 {
161 panic("demapPage(Addr) is not implemented.\n");
162 }
163
164 void dumpAll();
165
162 // Checkpointing
163 virtual void serialize(std::ostream &os);
164 virtual void unserialize(Checkpoint *cp, const std::string &section);
165
166 /** Give an entry id, read that tlb entries' tte */
167 uint64_t TteRead(int entry);
168
169};
170
171class ITB : public TLB
172{
173 public:
174 typedef SparcITBParams Params;
175 ITB(const Params *p) : TLB(p)
176 {
177 cacheEntry = NULL;
178 }
179
180 Fault translateAtomic(RequestPtr req, ThreadContext *tc);
181 void translateTiming(RequestPtr req, ThreadContext *tc,
182 Translation *translation);
183 private:
184 void writeSfsr(bool write, ContextType ct,
185 bool se, FaultTypes ft, int asi);
186 TlbEntry *cacheEntry;
187 friend class DTB;
188};
189
190class DTB : public TLB
191{
192 //DTLB specific state
193 protected:
194 uint64_t sfar;
195 public:
196 typedef SparcDTBParams Params;
197 DTB(const Params *p) : TLB(p)
198 {
199 sfar = 0;
200 cacheEntry[0] = NULL;
201 cacheEntry[1] = NULL;
202 }
203
204 Fault translateAtomic(RequestPtr req,
166 Fault translateAtomic(RequestPtr req,
205 ThreadContext *tc, bool write=false);
167 ThreadContext *tc, bool write=false, bool execute=false);
206 void translateTiming(RequestPtr req, ThreadContext *tc,
168 void translateTiming(RequestPtr req, ThreadContext *tc,
207 Translation *translation, bool write=false);
169 Translation *translation, bool write=false, bool execute=false);
208#if FULL_SYSTEM
209 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
210 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
211#endif
212 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
213
214 // Checkpointing
215 virtual void serialize(std::ostream &os);
216 virtual void unserialize(Checkpoint *cp, const std::string &section);
217
170#if FULL_SYSTEM
171 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
172 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
173#endif
174 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
175
176 // Checkpointing
177 virtual void serialize(std::ostream &os);
178 virtual void unserialize(Checkpoint *cp, const std::string &section);
179
180 /** Give an entry id, read that tlb entries' tte */
181 uint64_t TteRead(int entry);
182
218 private:
219 void writeSfsr(Addr a, bool write, ContextType ct,
220 bool se, FaultTypes ft, int asi);
221
222 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
223 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
224
225
226 TlbEntry *cacheEntry[2];
227 ASI cacheAsi[2];
228};
229
230}
231
232#endif // __ARCH_SPARC_TLB_HH__
183 private:
184 void writeSfsr(Addr a, bool write, ContextType ct,
185 bool se, FaultTypes ft, int asi);
186
187 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
188 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
189
190
191 TlbEntry *cacheEntry[2];
192 ASI cacheAsi[2];
193};
194
195}
196
197#endif // __ARCH_SPARC_TLB_HH__