tlb.hh (5034:6186ef720dd4) | tlb.hh (5358:e9acb84bbafb) |
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1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 25 unchanged lines hidden (view full) --- 34#include "arch/sparc/asi.hh" 35#include "arch/sparc/tlb_map.hh" 36#include "base/misc.hh" 37#include "config/full_system.hh" 38#include "mem/request.hh" 39#include "params/SparcDTB.hh" 40#include "params/SparcITB.hh" 41#include "sim/faults.hh" | 1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 25 unchanged lines hidden (view full) --- 34#include "arch/sparc/asi.hh" 35#include "arch/sparc/tlb_map.hh" 36#include "base/misc.hh" 37#include "config/full_system.hh" 38#include "mem/request.hh" 39#include "params/SparcDTB.hh" 40#include "params/SparcITB.hh" 41#include "sim/faults.hh" |
42#include "sim/sim_object.hh" | 42#include "sim/tlb.hh" |
43 44class ThreadContext; 45class Packet; 46 47namespace SparcISA 48{ 49 | 43 44class ThreadContext; 45class Packet; 46 47namespace SparcISA 48{ 49 |
50class TLB : public SimObject | 50class TLB : public BaseTLB |
51{ 52#if !FULL_SYSTEM 53 //These faults need to be able to populate the tlb in SE mode. 54 friend class FastInstructionAccessMMUMiss; 55 friend class FastDataAccessMMUMiss; 56#endif 57 58 //TLB state --- 88 unchanged lines hidden (view full) --- 147 148 149 void writeTagAccess(Addr va, int context); 150 151 public: 152 typedef SparcTLBParams Params; 153 TLB(const Params *p); 154 | 51{ 52#if !FULL_SYSTEM 53 //These faults need to be able to populate the tlb in SE mode. 54 friend class FastInstructionAccessMMUMiss; 55 friend class FastDataAccessMMUMiss; 56#endif 57 58 //TLB state --- 88 unchanged lines hidden (view full) --- 147 148 149 void writeTagAccess(Addr va, int context); 150 151 public: 152 typedef SparcTLBParams Params; 153 TLB(const Params *p); 154 |
155 void demapPage(Addr vaddr, uint64_t asn) 156 { 157 panic("demapPage(Addr) is not implemented.\n"); 158 } 159 |
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155 void dumpAll(); 156 157 // Checkpointing 158 virtual void serialize(std::ostream &os); 159 virtual void unserialize(Checkpoint *cp, const std::string §ion); 160 161 /** Give an entry id, read that tlb entries' tte */ 162 uint64_t TteRead(int entry); --- 60 unchanged lines hidden --- | 160 void dumpAll(); 161 162 // Checkpointing 163 virtual void serialize(std::ostream &os); 164 virtual void unserialize(Checkpoint *cp, const std::string §ion); 165 166 /** Give an entry id, read that tlb entries' tte */ 167 uint64_t TteRead(int entry); --- 60 unchanged lines hidden --- |