tlb.hh (4990:38d74405ddac) tlb.hh (4997:e7380529bd2d)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/asi.hh"
35#include "arch/sparc/tlb_map.hh"
36#include "base/misc.hh"
37#include "config/full_system.hh"
37#include "mem/request.hh"
38#include "sim/faults.hh"
39#include "sim/sim_object.hh"
40
41class ThreadContext;
42class Packet;
43
44namespace SparcISA
45{
46
47class TLB : public SimObject
48{
38#include "mem/request.hh"
39#include "sim/faults.hh"
40#include "sim/sim_object.hh"
41
42class ThreadContext;
43class Packet;
44
45namespace SparcISA
46{
47
48class TLB : public SimObject
49{
50#if !FULL_SYSTEM
51 //These faults need to be able to populate the tlb in SE mode.
52 friend class FastInstructionAccessMMUMiss;
53 friend class FastDataAccessMMUMiss;
54#endif
55
49 //TLB state
50 protected:
51 uint64_t c0_tsb_ps0;
52 uint64_t c0_tsb_ps1;
53 uint64_t c0_config;
54 uint64_t cx_tsb_ps0;
55 uint64_t cx_tsb_ps1;
56 uint64_t cx_config;

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178 DTB(const std::string &name, int size) : TLB(name, size)
179 {
180 sfar = 0;
181 cacheEntry[0] = NULL;
182 cacheEntry[1] = NULL;
183 }
184
185 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
56 //TLB state
57 protected:
58 uint64_t c0_tsb_ps0;
59 uint64_t c0_tsb_ps1;
60 uint64_t c0_config;
61 uint64_t cx_tsb_ps0;
62 uint64_t cx_tsb_ps1;
63 uint64_t cx_config;

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185 DTB(const std::string &name, int size) : TLB(name, size)
186 {
187 sfar = 0;
188 cacheEntry[0] = NULL;
189 cacheEntry[1] = NULL;
190 }
191
192 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
193#if FULL_SYSTEM
186 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
187 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
194 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
195 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
196#endif
188 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
189
190 // Checkpointing
191 virtual void serialize(std::ostream &os);
192 virtual void unserialize(Checkpoint *cp, const std::string &section);
193
194 private:
195 void writeSfsr(Addr a, bool write, ContextType ct,

--- 13 unchanged lines hidden --- 		197 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
198
199 // Checkpointing
200 virtual void serialize(std::ostream &os);
201 virtual void unserialize(Checkpoint *cp, const std::string &section);
202
203 private:
204 void writeSfsr(Addr a, bool write, ContextType ct,

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