tlb.hh (3603:714467743f9b) tlb.hh (3804:fa7a01dddc7a)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 17 unchanged lines hidden (view full) ---

26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#ifndef __ARCH_SPARC_TLB_HH__
32#define __ARCH_SPARC_TLB_HH__
33
34#include "arch/sparc/tlb_map.hh"
34#include "base/misc.hh"
35#include "mem/request.hh"
36#include "sim/faults.hh"
37#include "sim/sim_object.hh"
38
39class ThreadContext;
40
41namespace SparcISA
42{
35#include "base/misc.hh"
36#include "mem/request.hh"
37#include "sim/faults.hh"
38#include "sim/sim_object.hh"
39
40class ThreadContext;
41
42namespace SparcISA
43{
43 const int PAddrImplBits = 40;
44 const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
45
44
46 class TLB : public SimObject
47 {
48 public:
49 TLB(const std::string &name, int size) : SimObject(name)
50 {
51 }
45class TLB : public SimObject
46{
47 protected:
48 TlbMap lookupTable;;
49 typedef TlbMap::iterator MapIter;
50
51 TlbEntry *tlb;
52
53 int size;
54 int usedEntries;
55
56 enum FaultTypes {
57 OtherFault = 0,
58 PrivViolation = 0x1,
59 SideEffect = 0x2,
60 AtomicToIo = 0x4,
61 IllegalAsi = 0x8,
62 LoadFromNfo = 0x10,
63 VaOutOfRange = 0x20,
64 VaOutOfRangeJmp = 0x40
52 };
53
65 };
66
54 class ITB : public TLB
67 enum ContextType {
68 Primary = 0,
69 Secondary = 1,
70 Nucleus = 2
71 };
72
73
74 /** lookup an entry in the TLB based on the partition id, and real bit if
75 * real is true or the partition id, and context id if real is false.
76 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
77 * @param paritition_id partition this entry is for
78 * @param real is this a real->phys or virt->phys translation
79 * @param context_id if this is virt->phys what context
80 * @return A pointer to a tlb entry
81 */
82 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0);
83
84 /** Insert a PTE into the TLB. */
85 void insert(Addr vpn, int partition_id, int context_id, bool real,
86 const PageTableEntry& PTE);
87
88 /** Given an entry id, read that tlb entries' tag. */
89 uint64_t TagRead(int entry);
90
91 /** Give an entry id, read that tlb entries' tte */
92 uint64_t TteRead(int entry);
93
94 /** Remove all entries from the TLB */
95 void invalidateAll();
96
97 /** Remove all non-locked entries from the tlb that match partition id. */
98 void demapAll(int partition_id);
99
100 /** Remove all entries that match a given context/partition id. */
101 void demapContext(int partition_id, int context_id);
102
103 /** Remve all entries that match a certain partition id, (contextid), and
104 * va). */
105 void demapPage(Addr va, int partition_id, bool real, int context_id);
106
107 /** Checks if the virtual address provided is a valid one. */
108 bool validVirtualAddress(Addr va, bool am);
109
110 void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
111 bool se, FaultTypes ft, int asi);
112
113 void TLB::clearUsedBits();
114
115
116 public:
117 TLB(const std::string &name, int size);
118
119 // Checkpointing
120 virtual void serialize(std::ostream &os);
121 virtual void unserialize(Checkpoint *cp, const std::string &section);
122};
123
124class ITB : public TLB
125{
126 public:
127 ITB(const std::string &name, int size) : TLB(name, size)
55 {
128 {
56 public:
57 ITB(const std::string &name, int size) : TLB(name, size)
58 {
59 }
129 }
60
130
61 Fault translate(RequestPtr &req, ThreadContext *tc) const
62 {
63 //For now, always assume the address is already physical.
64 //Also assume that there are 40 bits of physical address space.
65 req->setPaddr(req->getVaddr() & PAddrImplMask);
66 return NoFault;
67 }
68 };
131 Fault translate(RequestPtr &req, ThreadContext *tc);
132 private:
133 void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
134 bool se, FaultTypes ft, int asi);
135};
69
136
70 class DTB : public TLB
137class DTB : public TLB
138{
139 public:
140 DTB(const std::string &name, int size) : TLB(name, size)
71 {
141 {
72 public:
73 DTB(const std::string &name, int size) : TLB(name, size)
74 {
75 }
142 }
76
143
77 Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const
78 {
79 //For now, always assume the address is already physical.
80 //Also assume that there are 40 bits of physical address space.
81 req->setPaddr(req->getVaddr() & ((1ULL << 40) - 1));
82 return NoFault;
83 }
84 };
144 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
145
146 private:
147 void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
148 bool se, FaultTypes ft, int asi);
149
150};
151
85}
86
87#endif // __ARCH_SPARC_TLB_HH__
152}
153
154#endif // __ARCH_SPARC_TLB_HH__