tlb.hh (12334:e0ab29a34764) tlb.hh (12406:86bde4a026b5)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 149 unchanged lines hidden (view full) ---

158 void
159 demapPage(Addr vaddr, uint64_t asn) override
160 {
161 panic("demapPage(Addr) is not implemented.\n");
162 }
163
164 void dumpAll();
165
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 149 unchanged lines hidden (view full) ---

158 void
159 demapPage(Addr vaddr, uint64_t asn) override
160 {
161 panic("demapPage(Addr) is not implemented.\n");
162 }
163
164 void dumpAll();
165
166 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
167 void translateTiming(RequestPtr req, ThreadContext *tc,
168 Translation *translation, Mode mode);
169 /** Stub function for compilation support with CheckerCPU. SPARC ISA
170 * does not support the Checker model at the moment
171 */
172 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
173 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
166 Fault translateAtomic(
167 RequestPtr req, ThreadContext *tc, Mode mode) override;
168 void translateTiming(
169 RequestPtr req, ThreadContext *tc,
170 Translation *translation, Mode mode) override;
171 Fault finalizePhysical(
172 RequestPtr req, ThreadContext *tc, Mode mode) const override;
174 Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
175 Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
176 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
177
178 // Checkpointing
179 void serialize(CheckpointOut &cp) const override;
180 void unserialize(CheckpointIn &cp) override;
181

--- 18 unchanged lines hidden --- 		173 Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
174 Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
175 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
176
177 // Checkpointing
178 void serialize(CheckpointOut &cp) const override;
179 void unserialize(CheckpointIn &cp) override;
180

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