tlb.hh (10905:a6ca6831e775) tlb.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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171 */
172 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
173 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
174 Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
175 Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
176 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
177
178 // Checkpointing
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 162 unchanged lines hidden (view full) ---

171 */
172 Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
173 Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
174 Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
175 Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
176 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
177
178 // Checkpointing
179 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
180 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
179 void serialize(CheckpointOut &cp) const override;
180 void unserialize(CheckpointIn &cp) override;
181
182 /** Give an entry id, read that tlb entries' tte */
183 uint64_t TteRead(int entry);
184
185 private:
186 void writeSfsr(Addr a, bool write, ContextType ct,
187 bool se, FaultTypes ft, int asi);
188
189 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
190 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
191
192
193 TlbEntry *cacheEntry[2];
194 ASI cacheAsi[2];
195};
196
197}
198
199#endif // __ARCH_SPARC_TLB_HH__
181
182 /** Give an entry id, read that tlb entries' tte */
183 uint64_t TteRead(int entry);
184
185 private:
186 void writeSfsr(Addr a, bool write, ContextType ct,
187 bool se, FaultTypes ft, int asi);
188
189 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
190 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
191
192
193 TlbEntry *cacheEntry[2];
194 ASI cacheAsi[2];
195};
196
197}
198
199#endif // __ARCH_SPARC_TLB_HH__