1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 35 unchanged lines hidden (view full) --- 44class Packet; 45 46namespace SparcISA 47{ 48 49class TLB : public BaseTLB 50{ 51#if !FULL_SYSTEM |
52 // These faults need to be able to populate the tlb in SE mode. |
53 friend class FastInstructionAccessMMUMiss; 54 friend class FastDataAccessMMUMiss; 55#endif 56 |
57 // TLB state |
58 protected: 59 // Only used when this is the data TLB. 60 uint64_t sfar; 61 uint64_t c0_tsb_ps0; 62 uint64_t c0_tsb_ps1; 63 uint64_t c0_config; 64 uint64_t cx_tsb_ps0; 65 uint64_t cx_tsb_ps1; --- 85 unchanged lines hidden (view full) --- 151 152 Fault translateInst(RequestPtr req, ThreadContext *tc); 153 Fault translateData(RequestPtr req, ThreadContext *tc, bool write); 154 155 public: 156 typedef SparcTLBParams Params; 157 TLB(const Params *p); 158 |
159 void 160 demapPage(Addr vaddr, uint64_t asn) |
161 { 162 panic("demapPage(Addr) is not implemented.\n"); 163 } 164 165 void dumpAll(); 166 167 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); 168 void translateTiming(RequestPtr req, ThreadContext *tc, --- 29 unchanged lines hidden --- |