1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 64 unchanged lines hidden (view full) --- 73 }; 74 75 enum ContextType { 76 Primary = 0, 77 Secondary = 1, 78 Nucleus = 2 79 }; 80 |
81 enum TsbPageSize { 82 Ps0, 83 Ps1 84 }; 85 public: |
86 /** lookup an entry in the TLB based on the partition id, and real bit if 87 * real is true or the partition id, and context id if real is false. 88 * @param va the virtual address not shifted (e.g. bottom 13 bits are 0) 89 * @param paritition_id partition this entry is for 90 * @param real is this a real->phys or virt->phys translation 91 * @param context_id if this is virt->phys what context |
92 * @param update_used should ew update the used bits in the entries on not 93 * useful if we are trying to do a va->pa without mucking with any state for 94 * a debug read for example. |
95 * @return A pointer to a tlb entry 96 */ |
97 TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0, 98 bool update_used = true); 99 protected: |
100 /** Insert a PTE into the TLB. */ 101 void insert(Addr vpn, int partition_id, int context_id, bool real, 102 const PageTableEntry& PTE, int entry = -1); 103 104 /** Given an entry id, read that tlb entries' tag. */ 105 uint64_t TagRead(int entry); 106 107 /** Remove all entries from the TLB */ --- 58 unchanged lines hidden (view full) --- 166 { 167 cacheEntry[0] = NULL; 168 cacheEntry[1] = NULL; 169 } 170 171 Fault translate(RequestPtr &req, ThreadContext *tc, bool write); 172 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); 173 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); |
174 void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); |
175 176 private: 177 void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 178 bool se, FaultTypes ft, int asi); 179 void writeTagAccess(ThreadContext *tc, Addr va, int context); 180 |
181 uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, 182 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config); 183 184 |
185 TlbEntry *cacheEntry[2]; 186 ASI cacheAsi[2]; 187}; 188 189} 190 191#endif // __ARCH_SPARC_TLB_HH__ |