1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 24 unchanged lines hidden (view full) --- 33 34#include "arch/sparc/tlb_map.hh" 35#include "base/misc.hh" 36#include "mem/request.hh" 37#include "sim/faults.hh" 38#include "sim/sim_object.hh" 39 40class ThreadContext; |
41class Packet; |
42 43namespace SparcISA 44{ 45 46class TLB : public SimObject 47{ 48 protected: 49 TlbMap lookupTable;; --- 88 unchanged lines hidden (view full) --- 138class DTB : public TLB 139{ 140 public: 141 DTB(const std::string &name, int size) : TLB(name, size) 142 { 143 } 144 145 Fault translate(RequestPtr &req, ThreadContext *tc, bool write); |
146 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); 147 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); |
148 149 private: 150 void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 151 bool se, FaultTypes ft, int asi); 152 153}; 154 155} 156 157#endif // __ARCH_SPARC_TLB_HH__ |